M29DW128F60NF1 STMICROELECTRONICS [STMicroelectronics], M29DW128F60NF1 Datasheet - Page 33

• Manufacturer Part Number: M29DW128F60NF1
• Description: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29DW128F
6.2.1
After programming has started, Bus Read operations in the Bank being programmed output the
Status Register content, while Bus Read operations to the other Bank output the contents of
the memory array. Fast program commands can be suspended and then resumed by issuing a
Program Suspend command and a Program Resume command, respectively (see
Suspend command
After the fast program operation has completed, the memory will return to the Read mode,
unless an error has occurred. When an error occurs Bus Read operations to the Bank where
the command was issued will continue to output the Status Register. A Read/Reset command
must be issued to reset the error condition and return to Read mode. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in
Endurance
Write to Buffer and Program command
The Write to Buffer and Program Command makes use of the device’s 64-Byte Write Buffer to
speed up programming. 32 Words/64 Bytes can be loaded into the Write Buffer. Each Write
Buffer has the same A5-A22 addresses.The Write to Buffer and Program command
dramatically reduces system programming time compared to the standard non-buffered
Program command.
When issuing a Write to Buffer and Program command, the V
High, V
See
Five successive steps are required to issue the Write to Buffer and Program command:
1.
2.
3.
4.
5.
All the addresses used in the Write to Buffer and Program operation must lie within the same
page.
To program the content of the Write Buffer, this command must be followed by a Write to Buffer
and Program Confirm command.
If an address is written several times during a Write to Buffer and Program operation, the
address/data counter will be decremented at each data load operation and the data will be
programmed to the last word loaded into the Buffer.
Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will
abort the Write to Buffer and Program.
Table 18
The Write to Buffer and Program command starts with two unlock cycles.
The third Bus Write cycle sets up the Write to Buffer and Program command. The setup
code can be addressed to any location within the targeted block.
The fourth Bus Write cycle sets up the number of Words to be programmed. Value n is
written to the same block address, where n+1 is the number of Words to be programmed.
n+1 must not exceed the size of the Write Buffer or the operation will abort.
The fifth cycle loads the first address and data to be programmed.
Use n Bus Write cycles to load the address and data for each Word into the Write Buffer.
Addresses must lie within the range from the start address+1 to the start address + n-1.
Optimum performance is obtained when the start address corresponds to a 64 Byte
boundary. If the start address is not aligned to a 64 Byte boundary, the total programming
time is doubled.
IH
or raised to V
Cycles.
for details on typical Write to Buffer and Program times in both cases.
and
PPH
Program Resume command
.
Table 18: Program, Erase Times and Program, Erase
paragraphs.)
PP/
WP pin can be either held
6 Command Interface
Program
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