DS152 XILINX [Xilinx, Inc], DS152 Datasheet - Page 12

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DS152

Manufacturer Part Number
DS152
Description
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
Table 21: GTX Transceiver Reference Clock Switching Characteristics
X-Ref Target - Figure 3
Table 22: GTX Transceiver User Clock Switching Characteristics
DS152 (v2.10) October18, 2010
Advance Product Specification
Notes:
1.
2.
3.
F
T
T
T
T
T
F
F
T
T
T
T
Symbol
Symbol
GCLK
RCLK
FCLK
DCREF
LOCK
PHASE
TXOUT
RXREC
RX
RX2
TX
TX2
Clocking must be implemented as described in the Virtex-6 FPGA GTX Transceivers User Guide.
406.25 MHz when the RX elastic buffer is bypassed.
406.25 MHz when the TX buffer is bypassed.
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
RXUSRCLK2 maximum frequency
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
Description
Description
80%
20%
T
FCLK
Figure 3: Reference Clock Timing Parameters
Internal 20-bit data path
Internal 16-bit data path
Internal 20-bit data path
Internal 16-bit data path
1 byte interface
2 byte interface
4 byte interface
1 byte interface
2 byte interface
4 byte interface
20% – 80%
80% – 20%
Transceiver PLL only
Initial PLL lock
Lock to data after PLL has locked
to the reference clock
Conditions
T
www.xilinx.com
RCLK
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Conditions
(1)
412.5
412.5
406.25
206.25
406.25
206.25
412.5
412.5
330
330
376
376
-3
(2)
(3)
412.5
412.5
406.25
206.25
406.25
206.25
412.5
412.5
62.5
Min
330
330
376
376
45
-2
Speed Grade
(2)
(3)
All Speed Grades
ds152_05_042109
156.25
156.25
Typ
200
200
312.5
312.5
312.5
312.5
312.5
312.5
312.5
312.5
50
250
250
-1
Max
650
200
55
250
250
250
250
250
250
250
125
250
250
250
125
-1L
1
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
ps
ps
µs
%
12

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