DS152 XILINX [Xilinx, Inc], DS152 Datasheet - Page 43

• Manufacturer Part Number: DS152
• Description: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Table 57: DSP48E1 Switching Characteristics (Cont’d)
Configuration Switching Characteristics
Table 58: Configuration Switching Characteristics
DS152 (v2.10) October18, 2010
Advance Product Specification
Clock to Outs from Input Register Clock to Output Pins
T
T
T
T
Clock to Outs from Input Register Clock to Cascading Output Pins
T
T
MULTSIGNOUT}_{AREG, BREG}_MULT
T
MULTSIGNOUT}_{AREG, BREG}
T
MULTSIGNOUT}_DREG_MULT
T
MULTSIGNOUT}_CREG
Maximum Frequency
F
F
F
F
F
F
F
F
Power-up Timing Characteristics
T
T
T
T
DSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT
DSPCKO_{P, CARRYOUT}_{AREG, BREG}
DSPCKO_{P, CARRYOUT}_CREG
DSPCKO_{P, CARRYOUT}_DREG_MULT
DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}
DSPCKO_{PCOUT, CARRYCASCOUT,
DSPCKO_{PCOUT, CARRYCASCOUT,
DSPCKO_{PCOUT, CARRYCASCOUT,
DSPCKO_{PCOUT, CARRYCASCOUT,
MAX
MAX_PATDET
MAX_MULT_NOMREG
MAX_MULT_NOMREG_PATDET
MAX_PREADD_MULT_NOADREG
MAX_PREADD_MULT_NOADREG_PATDET
MAX_NOPIPELINEREG
MAX_NOPIPELINEREG_PATDET
PL
POR
ICCK
PROGRAM
(1)
(1)
Symbol
Symbol
Program Latency
Power-on-Reset
CCLK (output) delay
Program Pulse Width
Description
CLK (AREG, BREG) to {P, CARRYOUT}
output using multiplier
CLK (AREG, BREG) to {P, CARRYOUT}
output not using multiplier
CLK (CREG) to {P, CARRYOUT} output
CLK (DREG) to {P, CARRYOUT} output
CLK (AREG, BREG) to {P, CARRYOUT}
output
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
CLK (DREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
CLK (CREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
With all registers used
With pattern detector
Two register multiply without MREG
Two register multiply without MREG
with pattern detect
Without ADREG
Without ADREG with pattern detect
Without pipeline registers (MREG,
ADREG)
Without pipeline registers (MREG,
ADREG) with pattern detect
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Description
15/55
400
250
-3
5
15/55
400
250
Speed Grade
-2
5
3.97
1.70
1.70
3.89
0.66
4.05
1.79
3.98
1.78
600
551
356
327
398
398
266
250
-3
15/55
400
250
-1
5
4.52
1.93
1.93
4.44
0.76
4.63
2.03
4.54
2.03
540
483
311
286
347
347
233
219
-2
Speed
15/55
5.36
2.27
2.27
5.25
0.89
5.49
2.40
5.38
2.40
450
408
262
241
292
292
196
184
400
250
-1L
-1
5
6.20
2.65
2.80
6.07
1.01
6.39
2.84
6.26
2.99
410
356
224
211
254
254
171
160
-1L
ms, Min/Max
ms, Max
ns, Min
ns, Min
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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