MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 51

• Manufacturer Part Number: MC68HC711D3CFB2
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.3.1 Software Interrupt (SWI)
The SWI is executed the same as any other instruction and takes precedence over interrupts only if the
other interrupts are masked (with I and X bits in the CCR set). SWI execution is similar to that of the
maskable interrupts in that it sets the I bit, stacks the central processor unit (CPU) registers, etc.
4.3.2 Illegal Opcode Trap
Since not all possible opcodes or opcode sequences are defined, an illegal opcode detection circuit has
been included in the MCU. When an illegal opcode is detected, an interrupt is required to the illegal
opcode vector. The illegal opcode vector should never be left uninitialized.
4.3.3 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) provides a programmable periodic interrupt. This interrupt is maskable by
either the I bit in the CCR or the RTI enable (RTII) bit of the timer interrupt mask register 2 (TMSK2). The
rate is based on the MCU E clock and is software selectable to the E ÷ 2
See PACTL, TMSK2, and TFLG2 register descriptions in
status bit information.
4.3.4 Interrupt Mask Bits in the CCR
Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable interrupts and XIRQ. After
minimum system initialization, software may clear the X bit by a TAP instruction, thus enabling XIRQ
interrupts. Thereafter software cannot set the X bit. So, an XIRQ interrupt is effectively a non-maskable
interrupt. Since the operation of the I bit related interrupt structure has no effect on the X bit, the internal
XIRQ pin remains effectively non-masked. In the interrupt priority logic, the XIRQ interrupt is a higher
priority than any source that is maskable by the I bit. All I bit related interrupts operate normally with their
own priority relationship.
Freescale Semiconductor
The SWI instruction cannot be executed as long as another interrupt is
pending. However, once the SWI instruction has begun, no other interrupt
can be honored until the first instruction in the SWI service routine is
completed.
SP –
SP –
SP –
SP –
SP –
SP –
SP – 1
SP – 2
SP – 3
Figure 4-3. Interrupt Stacking Order
SP
4
5
6
7
8
9
MC68HC711D3 Data Sheet, Rev. 2.1
STACK
ACCA
ACCB
CCR
PCH
PCL
IXH
IXL
IYL
IYH
NOTE
— SP BEFORE INTERRUPT
— SP AFTER INTERRUPT
Chapter 8 Programmable Timer
13
, E ÷ 2
14
, E ÷ 2
for control and
15
, or E ÷ 2
Interrupts
16
51
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