MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 97

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MC68HC711D3CFB2

Manufacturer Part Number
MC68HC711D3CFB2
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
PR1 and PR0 — Timer Prescaler Select Bits
8.4.10 Timer Interrupt Flag 2 Register
The timer interrupt flag 2 register (TFLG2) bits indicate when certain timer system events have occurred.
Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same
position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time (Periodic) Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits 3–0 — Not implemented
Freescale Semiconductor
These bits are used to select the prescaler divide-by ratio. In normal modes, PR1 and PR0 can be
written once only, and the write must be within 64 cycles after reset. Refer to
timing values.
Set when TCNT changes from $FFFF to $0000
Refer to
Refer to
Refer to
Always read 0.
8.5 Real-Time
8.7 Pulse
8.7 Pulse
Address:
Reset:
Read:
Write:
Accumulator.
Accumulator.
$0025
Bit 7
TOF
0
Figure 8-15. Timer Interrupt Flag 2 Register (TFLG2)
Interrupt.
RTIF
6
0
MC68HC711D3 Data Sheet, Rev. 2.1
PR1 and PR0
Table 8-4. Timer Prescale
PAOVF
0 0
0 1
1 0
1 1
5
0
PAIF
4
0
Prescaler
3
0
0
16
1
4
8
2
0
0
1
0
0
Table 8-4
Output Compare (OC)
Bit 0
0
0
for specific
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