M30622ECTFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622ECTFP Datasheet - Page 59

• Manufacturer Part Number: M30622ECTFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Interrupt
Interrupt Sequence
Figure 1.14.4. Interrupt response time
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
Interrupt Response Time
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.14.4 shows the interrupt response time.
dress 00000
in the temporary register (Note) within the CPU.
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Tentative Specifications REV.A
Interrupt request generated
S
pecifications in this manual are tentative and subject to change.
16
.
Instruction
(a)
Interrupt response time
Interrupt request acknowledged
Interrupt sequence
(b)
59
interrupt routine
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Instruction in
Mitsubishi microcomputers
M16C / 62T Group
Time