M30622M4 MITSUBISHI [Mitsubishi Electric Semiconductor], M30622M4 Datasheet - Page 146

• Manufacturer Part Number: M30622M4
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

UART2 Special Mode Register 2
146
Figure 1.19.30. Functional block diagram for I
P7
P7
P7
Functions available in I
Bit 3 of the UART2 special mode register 2 (address 0376
this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the
instant when the arbitration loss detection flag is set to "1".
Bit 1 of the UART2 special mode register 2 (address 0376
With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (0376
"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to
"0" frees the output fixed to "L".
0
1
/TXD
2
/RXD
/CLK
2
/SDA
2
2
/SCL
Noize
Filter
Noize
Filter
Noize
Filter
Selector
Selector
Selector
UART2
2
C mode are shown in Figure 1.19.30 — a functional block diagram.
Falling edge
detection
Start condition detection
Stop condition detection
IICM=1
IICM=0
Timer
IICM=1
IICM=0
I/0
UART2
I/0
UART2
D
T
SDHI
Q
IICM=1
IICM=0
Timer
I/0
L-synchronous
output enabling bit
IICM=1
IICM=0
ALS
R
delay
Arbitration
Data register
Internal clock
External clock
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
Port reading
Transmission register
SWC2
R
S
UART2
2
S
R
C mode
CLK
control
16
Reception register
Q
Falling of 9th pulse
) is used as the SCL wait output bit. Setting this bit to
Bus
busy
UART2
UART2
SWC
Bus collision
detection
9th pulse
D
D
16
T
T
1
Q
Q
16
of the direction register.
) is used as the SDA output stop bit. Setting
) is used as the clock synchronization bit.
IICM=0
or IICM2=1
IICM=0
or
IICM2=1
ACK
IICM=1
and IICM2=0
IICM=1
and IICM2=0
IICM=1
IICM=0
NACK
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus collision/start, stop condition detection
interrupt request
UART2 reception/ACK interrupt request
DMA1 request
To DMA0
UART2 transmission/
NACK interrupt
request
To DMA0, DMA1
Mitsubishi microcomputers
M16C / 62 Group