71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 111

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

5.2
Table 76
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
Name
ADC_E
ADC_DIV
BCURR
BSENSE[7:0]
CE_E
CE_LCTN[5:0]
CHIP_ID[15:8]
CHIP_ID[7:0]
CHOP_E[1:0]
I/O RAM Map – Alphabetical Order
lists I/O RAM bits and registers in alphabetical order.
Location
2885[7:0]
2109[5:0]
2300[7:0]
2301[7:0]
2106[3:2]
2704[4]
2200[5]
2704[3]
2106[0]
Table 76: I/O RAM Map – Functional Order
Rst Wk Dir
31 31 R/W
0
0
0
–
0
0
0
0
0
0
0
–
0
0
0
0
R/W Enables ADC and VREF. When disabled, reduces bias current.
R/W
R/W Connects a 100 µA load to the battery selected by TEMP_BSEL.
R/W CE enable.
R/W
R
R
R
Description
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
The resulting ADC and FIR clock is as shown below.
The result of the battery measurement. See
CE program location. The starting address for the CE program is
1024*CE_LCTN.
These bytes contain the chip identification.
Chop enable for the reference bandgap circuit. The value of CHOP changes
on the rising edge of MUXSYNC according to the value in CHOP_E:
1
00 = toggle
except at the mux sync edge at the end of an accumulation interval.
0 = MCK/4
1 = MCK/8
1
ADC_DIV = 0
ADC_DIV = 1
01 = positive
MCK
6.291456 MHz
1.572864 MHz
0.786432 MHz
PLL_FAST = 0
10 = reversed
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.6 71M654x Battery Monitor.
11 = toggle
19.660800 MHz
PLL_FAST = 1
4.9152 MHz
2.4576 MHz