71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 59

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

2.5.8 Digital I/O and LCD Segment Drivers
2.5.8.1 General Information
The 71M6541D/F/G and 71M6542F/G combine most DIO pins with LCD segment drivers. Each
SEG/DIO pin can be configured as a DIO pin or as a segment (SEG) driver pin.
On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until
they are configured as desired under MPU control. The pin function can be configured by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO.
Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs.
the internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0].
If more than one input is connected to the same resource, the resources are combined using a logical OR.
PORT_E.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
Value in DIO_Rn[2:0]
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits
UART1_TX
Table 48
DIO5
0
1
2
3
4
OPT_BB
0
1
0
1
UART1_RX
OPT_TXINV
OPT_TXMOD=0
Figure 19: Optical Interface (UART1)
(71M6541D/F/G) and
OPT_TXMOD
DIO55
OPT_FDC
A
OPT_RXDIS
Resource Selected for SEGDIOn or PB Pin
None
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (INT0)
1
0
EN
MOD
2
DUTY
VARPULSE
WPULSE
DIO51
B
2
0
3
1
Table 52
OPT_TXE[1:0]
A
B
71M6541D/F/G and 71M6542F/G Data Sheet
SEG55
SEG51
SEG5
OPT_FDC=2 (25%)
OPT_TXMOD=1,
LCD_MAP[51]
LCD_MAP[5]
LCD_MAP[55]
(71M6542F/G).
1
0
1
0
1
0
1/38kHz
Internal
Figure
SEGDIO55/
OPT_RX
SEGDIO51/
OPT_TX
SEGDIO5/TX2
16.
V3P3
Table 47
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