71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 63

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

5 dedicated SEG segment pins are available:
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that are listed under combined SEG/DIO shared pins (SEGDIO26/COM5,
SEGDIO27/COM4).
Thus, in a configuration where none of these pins are used as DIOs, there can be up to 55 LCD segment
pins with 4 commons, or 53 LCD segment pins with 6 commons. And in a configuration where LCD
segment pins are not used, there can be up to 50 DIO pins.
Example: SEGDIO12 (see pin 32 in
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured as
an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5 of
LCD_SEG12.
The configuration for pins SEGDIO16 to SEGDIO31 is shown in
SEGDIO32 to SEGDIO45 is shown in
pins. The configuration for pins SEGDIO51 to SEGDIO55 is shown in
2.5.8.3 Digital I/O for the 71M6542F/G
A total of 55 combined SEG/DIO pins are available for the 71M6542D/F. These pins can be categorized
as follows:
35 combined DIO/LCD segment pins:
15 combined DIO/LCD segment pins shared with other functions:
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see
Table
SEGDIO
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Pin #
SEGDIO4…SEGDIO5 (2 pins)
SEGDIO9…SEGDIO25 (17 pins)
SEGDIO28…SEGDIO35 (8 pins)
SEGDIO40…SEGDIO45 (6 pins)
SEGDIO52…SEGDIO53 (2 pins)
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)
SEGDIO8/DI (1 pin)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 pins)
Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT (2 pins)
Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F/G)
47)
45
0
0
0
0
4
–
P0 (SFR 0x80)
P0 (SFR 0x80)
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
44
1
1
1
1
5
–
43
Y
2
2
2
2
6
Table
Table 54.
42
Y
3
3
3
3
7
52) is configured as a DIO output pin with a value of 1 (high) by
41
Y
4
4
4
0
4
P1 (SFR 0x90)
P1 (SFR 0x0)
SEG46 through SEG50 cannot be configured as DIO
39
5
1
5
Y
5
5
38
Y
6
6
6
2
6
71M6541D/F/G and 71M6542F/G Data Sheet
37
Y
7
7
7
3
7
Table
36
8
Y
0
8
0
4
P2 (SFR 0xA0)
P2 (SFR 0xA0)
LCD_MAP[15:8] (I/O RAM 0x240A)
Table 55.
53, the configuration for pins
35
Y
9
1
9
1
5
10
34
10
2
2
6
Y
11
33
11
Y
3
3
7
12
32
12
4
0
4
–
P3 (SFR 0xB0)
P3 (SFR 0xB0)
13
31
13
5
1
5
–
14
30
14
6
2
6
–
15
29
15
3
7
7
–