71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 41

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

the corresponding interrupt flag can be individually enabled or disabled by the interrupt enable bits in the
IEN0 (SFR 0xA8), IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A).
Figure
Referring to
Internal Sources) or can originate from other parts of the 71M654x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of
Table 27
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown in
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from interrupt instruction, RETI. When a RETI instruction is performed, the
processor returns to the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, and then samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the
interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address, if the
following conditions are met:
•
•
•
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
•
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
The interrupt enable registers: IEN0, IEN1 and IEN2 (see
The Timer/Counter control registers, TCON and T2CON (see
Table
The interrupt request register, IRCON (see
The interrupt priority registers: IP0 and IP1 (see
16 shows the device interrupt structure.
(i.e., EX0-EX6).
29 and
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
IEN1[7]
IEN1[6]
IEN1[5]
IEN1[4]
IEN1[3]
Figure
Bit
Bit
Table
16, interrupt sources can originate from within the 80515 MPU core (referred to as
30).
Symbol
Symbol
WDT
EAL
EX1
EX0
EX6
EX5
EX4
ES0
ET1
ET0
–
–
–
Table 26: The IEN0 Bit Functions (SFR 0xA8)
Table 27: The IEN1 Bit Functions (SFR 0xB8)
EAL = 0 disables all interrupts.
Not used for interrupt control.
Not Used.
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1: DIO status change
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0: DIO status change
Not used.
Not used.
EX6 = 0 disables external interrupt 6:
XFER_BUSY, RTC_1S, RTC_1M or RTC_T
EX5 = 0 disables external interrupt 5: EEPROM or SPI
EX4 = 0 disables external interrupt 4: VSTAT
Table
Table
31).
36).
71M6541D/F/G and 71M6542F/G Data Sheet
Table 26, Table 27
Function
Function
Figure
and
16, and in
Table
Table
28).
Table 26
38. Once
and