71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 61

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

5 dedicated SEG segment pins are available:
There are four dedicated common segment outputs (COM0…COM3) plus the two additional shared common
segment outputs that are listed under combined SEG/DIO shared pins (SEGDIO26/COM5,
SEGDIO27/COM4).
Thus, in a configuration where none of these pins are used as DIOs, there can be up to 37 LCD segment
pins with 4 commons, or 35 LCD segment pins with 6 commons. And in a configuration where LCD
segment pins are not used, there can be up to 32 DIO pins.
The configuration for pins SEGDIO19 to SEGDIO27 is shown in
SEGDIO36-39 and SEGDIO44-45 is shown in
The configuration for pins SEGDIO51 and SEGDIO55 is shown in
2.5.8.2 Digital I/O for the 71M6541D/F/G
A total of 32 combined SEG/DIO pins plus 5 SEG outputs are available for the 71M6541D/F/G. These
pins can be categorized as follows:
17 combined SEG/DIO segment pins:
15 combined SEG/DIO segment pins shared with other functions:
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see
Table
o
o
o
o
o
o
o
o
o
o
o
o
o
Table 48: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F/G)
SEGDIO4…SEGDIO5 (2 pins)
SEGDIO9…SEGDIO14 (6 pins)
SEGDIO19…SEGDIO25 (7 pins)
SEGDIO44…SEGDIO45 (2 pins)
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO6/XPULSE, SEGDIO7/YPULSE (2 pins)
SEGDIO8/DI (1 pin)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
ICE Inteface pins: SEG48/E_RXTX, SEG49/E_TCLK, SEG50/E_RST (3 pins)
Test Port pins: SEG46/TMUX2OUT, SEG47/TMUXOUT (2 pins)
47)
31
0
0
0
0
4
–
P0 (SFR 0x80)
P0 (SFR 0x80)
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_SEG0[5:0] to LCD_SEG14[5:0] (I/O RAM 0x2410[5:0] to 0x241E[5:0]
30
1
1
1
1
5
–
29
Y
2
2
2
2
6
28
Y
3
3
3
3
7
27
Y
4
4
4
0
4
Table
P1 (SFR 0x90)
P1 (SFR 0x90)
26
5
5
5
1
5
Y
50. SEG46 to SEG50 cannot be configured for DIO.
25
Y
6
6
6
2
6
24
71M6541D/F/G and 71M6542F/G Data Sheet
Y
7
7
7
3
7
Table
23
Table
8
Y
0
8
0
4
P2 (SFR 0xA0)
P2 (SFR 0xA0)
LCD_MAP[14:8] (I/O RAM 0x240A)
22
49, and the configuration for pins
Y
9
1
9
1
5
51.
21
10
10
2
2
6
Y
20
11
11
Y
3
3
7
19
12
12
4
0
4
–
P3 (SFR 0xB0)
P3 (SFR 0xB0)
18
13
13
5
1
5
–
17
14
14
6
2
6
–
15
–
–
–
–
–
–