71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 19

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

Table 4
All listed registers are 0 after reset and wake from battery modes, and are readable and writable.
2.2.3 Delay Compensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that
phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.
Where f is the frequency of the input signal, T = 1/f and t
voltage.
Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the
other one for current) controlled to sample simultaneously. Maxim’s Teridian Single-Converter
Technology, however, exploits the 32-bit signal processing capability of its CE to implement “constant
delay” all-pass filters. The all-pass filter corrects for the conversion time difference between the voltage
and the corresponding current samples that are obtained with a single multiplexed A/D converter.
The “constant delay” all-pass filter provides a broad-band delay 360
the difference in sample time between the voltage and the current of a given phase. This digital filter
does not affect the amplitude of the signal, but provides a precisely controlled phase response.
The recommended ADC multiplexer sequence samples the current first, immediately followed by
sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to
Name
MUX10_SEL[3:0]
Refer to
MUX0_SEL[3:0]
MUX1_SEL[3:0]
MUX2_SEL[3:0]
MUX3_SEL[3:0]
MUX4_SEL[3:0]
MUX5_SEL[3:0]
MUX6_SEL[3:0]
MUX7_SEL[3:0]
MUX8_SEL[3:0]
MUX9_SEL[3:0]
MUX_DIV[3:0]
FIR_LEN[1:0]
PLL_FAST
ADC_DIV
DIFFA_E
DIFFB_E
RMT_E
PRE_E
Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],
MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.
Refer to
71M6542F/G.
summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC.
Table 76
Table 1
starting on page
Location
2105[3:0]
2105[7:4]
2104[3:0]
2104[7:4]
2103[3:0]
2103[7:4]
2102[3:0]
2102[7:0]
2101[3:0]
2101[7:0]
2100[3:0]
2100[7:4]
210C[1]
210C[4]
210C[5]
2200[5]
2200[4]
2709[3]
2704[5]
and
Table 4: Multiplexer and ADC Configuration Bits
Table 2
Description
Selects the ADC input converted during time slot 0.
Selects the ADC input converted during time slot 1.
Selects the ADC input converted during time slot 2.
Selects the ADC input converted during time slot 3.
Selects the ADC input converted during time slot 4.
Selects the ADC input converted during time slot 5.
Selects the ADC input converted during time slot 6.
Selects the ADC input converted during time slot 7.
Selects the ADC input converted during time slot 8.
Selects the ADC input converted during time slot 9.
Selects the ADC input converted during time slot 10.
Controls the rate of the ADC and FIR clocks.
The number of ADC time slots in each multiplexer frame (maximum = 11).
Controls the speed of the PLL and MCK.
Determines the number of ADC cycles in the ADC decimation FIR filter.
Enables the differential configuration for analog input pins IAP-IAN.
Enables the differential configuration for analog input pins IBP-IBN.
Enables the remote sensor interface transforming pins IBP-IBN into a
digital balanced differential pair for communications with the 71M6x01
sensor.
Enables the 8x pre-amplifier.
111
φ
for the settings that are applicable to the 71M6541D/F/G and
=
for more complete details about these I/O RAM locations.
t
delay
T
⋅
360
o
=
t
delay
delay
⋅
71M6541D/F/G and 71M6542F/G Data Sheet
is the sampling delay between current and
f
⋅
360
o
o
– θ, which is precisely matched to