71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 38

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

71M6541D/F/G and 71M6542F/G Data Sheet
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in
S0CON[7]
S0CON[6]
S0CON[5]
S0CON[4]
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
S1CON[7]
S1CON[5]
S1CON[4]
S1CON[3]
S1CON[2]
S1CON[1]
S1CON[0]
Bit
Bit
The proper way to clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
SM
SM21
REN1
TB81
RB81
TI1
RI1
Symbol
Symbol
Table 19
Table 20: The S1CON (UART1) Register (SFR 0x9B)
Table 19: The S0CON (UART0) Register (SFR 0x98)
and
Function
The SM0 and SM1 bits set the UART0 mode:
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Function
Sets the baud rate and mode for UART1.
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9
depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes A and B, it is the 9
RB81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Table 20,
SM
Mode
th
0
1
transmitted data bit in Mode A. Set or cleared by the MPU,
0
1
2
3
respectively, and the PCON register shown in
Mode
N/A
8-bit UART
9-bit UART
9-bit UART
A
B
Description
9-bit UART
8-bit UART
Description
th
th
data bit received. In Mode 1, SM20 is 0,
data bit received. In Mode B, if SM21 is 0,
SM0
0
0
1
1
variable
variable
Baud Rate
SM1
0
1
0
1
Table
21.