71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 48

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

71M6541D/F/G and 71M6542F/G Data Sheet
2.5
2.5.1 Physical Memory
2.5.1.1 Flash Memory
The device includes 128KB (71M6541G, 71M6542G), 64KB (71M6542F, 71M6541F) or 32KB
(71M6541D) of on-chip flash memory. The flash memory primarily contains MPU and CE program code.
It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU
copies these images to their respective locations.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[5:0] field (I/O RAM 0x2109[5:0])
defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at
1024*CE_LCTN[5:0].
Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W).
Flash Write Procedures
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4] key is correctly programmed, the MPU may write to the
flash memory. This is one of the non-volatile storage options available to the user in addition to external
EEPROM.
The flash program write enable bit, FLSH_PWE (SFR 0xB2[0]), differentiates 80515 data store instructions
(MOVX@DPTR,A) between Flash and XRAM writes. This bit is automatically cleared by hardware
after each byte write operation. Write operations to this bit are inhibited when interrupts are enabled.
If the CE bit is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless
FLSH_PSTWR (SFR 0xB2[2]) is set. This bit enables the “posted flash write” capability. FLSH_PSTWR has
no effect when CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time
interval between the CE code passes. During this delay time, the FLSH_PEND bit (SFR 0xB2[3]) is high, and
the MPU continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND
bit falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the
write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
•
•
Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).
Write the pattern 0xAA to the FLSH_ERASE register (SFR 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
On-Chip Resources
Access by
MPU
SPI
CE
Access
R/W/E
R/W/E
Type
R
Table 39: Flash Memory Access
Condition
W/E only if CE is disabled.
Access only when SFM is invoked (MPU halted).