71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 116

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

71M6541D/F/G and 71M6542F/G Data Sheet
Name
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
INTBITS
LCD_ALLCOM
LCD_BAT
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
LCD_CLK[1:0]
LCD_DAC[4:0]
LCD_E
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[7]
SFR F8[4]
SFR F8[3]
240D[4:0]
Location
2707[6:0]
2401[5:0]
2402[5:0]
2400[1:0]
2400[3]
2402[7]
2400[7]
Rst Wk Dir
0
–
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W Connects the LCD power supply to VBAT in all modes.
R/W
R/W
R/W
R/W
R
Description
Interrupt flags for external interrupts 2 and 6. These flags monitor the source
of the int6 and int2 interrupts (external interrupts to the MPU core). These
flags are set by hardware and must be cleared by the software interrupt
handler. The IEX2 (SFR 0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are
automatically cleared by the MPU core when it vectors to the interrupt
handler. IEX2 and IEX6 must be cleared by writing zero to their corresponding
bit positions in SFR 0xC0, while writing ones to the other bit positions that are
not being cleared.
Interrupt inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any memory and
are primarily intended for debug use.
Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP
bit is zero.
Identifies which segments connected to SEG23 and SEG22 should blink. 1
means ‘blink.’ The most significant bit corresponds to COM5, the least
significant, to COM0.
Sets the LCD clock frequency. Note: f
The LCD contrast DAC. This DAC controls the VLCD voltage and has an
output range of 2.5 V to 5 V. The VLCD voltage is
Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is
limited by V3P3SYS, VBAT, and whether LCD_BSTE = 1.
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs if their LCD_MAP bit is 1.
LCD_CLK LCD Clock Frequency
00
01
2
f
2
f
W
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
8
W
9
= 128 Hz
= 64 Hz
w
= 32768 Hz
LCD_CLK
10
11
LCD Clock Frequency
2
2
f
f
W
W
7
6
= 256 Hz
= 512 Hz