71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 32

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

Internal and External Memory Map
Table 10
71M6541D/F/G and 71M6542F/G Data Sheet
The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX
@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX
A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction).
† Memory size depends on IC. See
MOVX Addressing
There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to
the external data RAM.
In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight
lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA
SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the
external data RAM.
In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.
This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no
additional instructions are needed to set up the eight high ordered bits of the address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two
with direct access and two with paged access, to the entire external memory range.
Dual Data Pointer
The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that
is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS
register (DPS[0], SFR 0x92), chooses the active pointer. DPTR is selected when DPS[0] = 0 and DPTR1 is
selected when DPS[0] = 1.
The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers
are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected
DPTR for any activity.
0000-7FFF
0000-0BFF
2000-27FF
2800-287F
0000-00FF
Address
(hex)
By selecting the R80515 core in the Keil compiler project settings and by using the compiler directive
“MODC2”, dual data pointers are enabled in certain library routines.
compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and
restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.
DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster
The second data pointer may not be supported by certain compilers.
shows the address, type, use and size of the various memory components.
Flash Memory
Technology
Static RAM
Static RAM
Static RAM
Static RAM
Memory
Non-volatile
Non-volatile
Memory
(battery)
Volatile
Volatile
Volatile
2.5.1 Physical Memory
Type
Table 10: Memory Map
Program memory
for MPU and CE
RAM (I/O RAM)
RAM (I/O RAM)
External RAM
Configuration
Configuration
Internal RAM
(XRAM)
Name
for details.
Part of 80515 Core
MPU Program and
Shared by CE and
CE program (on 1
Hardware control
non-volatile data
Battery-buffered
Typical Usage
KB boundary)
memory
MPU
Memory Size
64/32 KB †
3 KB max.
5/3 KB †
(bytes)
2 KB
128
256