SST89V564RD-33-I-PJ SST [Silicon Storage Technology, Inc], SST89V564RD-33-I-PJ Datasheet

SST89V564RD-33-I-PJ

Manufacturer Part Number

SST89V564RD-33-I-PJ

Description

FlashFlex51 MCU

Manufacturer

SST [Silicon Storage Technology, Inc]

Datasheet

1.SST89V564RD-33-I-PJ.pdf (86 pages)

Current page: 1 of 86
Download datasheet (2Mb)

FEATURES:

• 8-bit 8051-Compatible Microcontroller (MCU)

• SST89E564RD/SST89E554RC Operation

• SST89V564RD/SST89V554RC Operation

• Total 1 KByte Internal RAM (256 Byte + 768 Byte)

• Dual Block SuperFlash EEPROM

• Support External Address Range up to 64

• Three High-Current Port 1 pins (16 mA each)

PRODUCT DESCRIPTION

The SST89E564RD, SST89V564RD, SST89E554RC, and

SST89V554RC are members of the FlashFlex51 family of 8-

bit microcontroller products designed and manufactured with

the state-of-the-art SuperFlash CMOS semiconductor pro-

cess technology. The devices use the 8051 instruction set

and are pin-for-pin compatible with standard 8051 microcon-

troller devices.

The device comes with 72/40 KByte of on-chip flash

EEPROM program memory using SST’s patented and pro-

prietary CMOS SuperFlash EEPROM technology with the

SST’s field-enhancing, tunneling injector, split-gate mem-

ory cells. The SuperFlash memory is partitioned into 2

independent program memory blocks. The primary Super-

Flash Block 0 occupies 64/32 KByte of internal program

memory space and the secondary SuperFlash Block 1

occupies 8 KByte of internal program memory space. The

8-KByte secondary SuperFlash block can be mapped to

the lowest location of the 64/32 KByte address space; it

can also be hidden from the program counter and used as

an independent EEPROM-like data memory. The flash

memory blocks can be programmed via a standard 87C5x

OTP EPROM programmer fitted with a special adapter and

S71207-04-000

with Embedded SuperFlash Memory

– Fully Software Compatible

– Development Toolset Compatible

– Pin-For-Pin Package Compatible

– 0 to 40 MHz at 5V

– 0 to 33 MHz at 3V

– SST89E564RD/SST89V564RD:

– SST89E554RC/SST89V554RC:

– Individual Block Security Lock with SoftLock

– Concurrent Operation during

– Memory Overlay for Interrupt Support

KByte of Program and Data Memory

64 KByte primary block + 8 KByte secondary

block (128-Byte sector size for both blocks)

32 KByte primary block + 8 KByte secondary

block (128-Byte sector size for both blocks)

In-Application Programming (IAP)

during IAP

SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC

12/03

SST89E/V564RD SST89E/VE554RC FlashFlex51 MCU

FlashFlex51 MCU

The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.

• Three 16-bit Timers/Counters

• Full-Duplex, Enhanced UART

• Eight Interrupt Sources at 4 Priority Levels

• Programmable Watchdog Timer (WDT)

• Programmable Counter Array (PCA)

• Four 8-bit I/O Ports (32 I/O Pins)

• Second DPTR register

• Low EMI Mode (Inhibit ALE)

• SPI Serial Interface

• Standard 12 Clocks per cycle, the device has an

• TTL- and CMOS-Compatible Logic Levels

• Brown-out Detection

• Low Power Modes

• PDIP-40, PLCC-44 and TQFP-44 Packages

• Temperature Ranges:

firmware for SST’s device. During the power-on reset, the

device can be configured as a slave to an external host for

source code storage or as a master to an external host for

an in-application programming (IAP) operation. The device

is designed to be programmed in-system and in-application

on the printed circuit board for maximum flexibility. The

device is pre-programmed with an example of the boot-

strap loader in the memory, demonstrating the initial user

program code loading or subsequent user code updating

via the IAP operation. An example bootstrap loader is avail-

able for the user’s reference and convenience only. SST

does not guarantee the functionality or the usefulness of

the sample bootstrap loader. Chip-Erase operations will

erase the pre-programmed sample code.

In addition to 72/40 KByte of SuperFlash EEPROM pro-

gram memory on-chip, the device can address up to 64

KByte of external program memory. In addition to 1024 x8

bits of on-chip RAM, up to 64 KByte of external RAM can

be addressed.

SST’s highly reliable, patented SuperFlash technology and

memory cell architecture have a number of important

advantages for designing and manufacturing flash

EEPROMs. These advantages translate into significant

cost and reliability benefits for our customers.

– Framing error detection

– Automatic address recognition

option to double the speed to 6 clocks per cycle.

– Power-down Mode with External Interrupt Wake-up

– Idle Mode

– Commercial (0°C to +70°C)

– Industrial (-40°C to +85°C)

These specifications are subject to change without notice.

Data Sheet

Related parts for SST89V564RD-33-I-PJ

SST89V564RD-33-I-PJ Summary of contents

Page 1

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC SST89E/V564RD SST89E/VE554RC FlashFlex51 MCU FEATURES: • 8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory – Fully Software Compatible – Development Toolset Compatible – Pin-For-Pin Package Compatible • SST89E564RD/SST89E554RC Operation – MHz at 5V • SST89V564RD/SST89V554RC Operation – ...

Page 2

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE OF CONTENTS PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES 1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 PIN ASSIGNMENTS 2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Data RAM Memory 3.4 Expanded Data RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 ...

Page 3

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 9.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1 Hard Lock 9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.4 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.2 Software Reset 10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.4 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.2 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.0 SYSTEM CLOCK AND CLOCK OPTIONS ...

Page 4

... FIGURE 2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 2-2: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 2-3: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 3-1: Program Memory Organization for SST89E564RD and SST89V564RD . . . . . . . . . . . . . . . . 11 FIGURE 3-2: Program Memory Organization for SST89E554RC and SST89V554RC . . . . . . . . . . . . . . . . 12 FIGURE 3-3: Internal and External Data Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIGURE 3-4: Dual Data Pointer Organization ...

Page 5

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC FIGURE 13-17: Block-Erase for SST89E/V564RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 FIGURE 13-18: Block-Erase for SST89E/V554RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 FIGURE 13-19: Sector-Erase FIGURE 13-20: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 FIGURE 13-21: Prog-SB1 / Prog-SB2 / Prog-SB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 FIGURE 13-22: Prog-SC0 / Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 FIGURE 13-23: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 LIST OF TABLES TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TABLE 3-1: SFCF Values for Program Memory Block Switching for SST89E/V564RD . . . . . . . . . . . . . . 12 TABLE 3-2: SFCF Values for Program Memory Block Switching for SST89E/V554RC ...

Page 6

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE 11-1: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 TABLE 12-1: Recommended Values for C1 and C2 by Crystal Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 12-2: Clock Doubling Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 13-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TABLE 13-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TABLE 13-3: AC Conditions of Test TABLE 13-4: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TABLE 13-5: Pin Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TABLE 13-6: DC Electrical Characteristics for SST89E5x4Rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TABLE 13-7: DC Electrical Characteristics for SST89V5x4Rx ...

Page 7

... FUNCTIONAL BLOCKS UNCTIONAL LOCK IAGRAM Oscillator SuperFlash EEPROM Primary 32K/64K x8 Secondary 1. 64K x8 for SST89E564RD and SST89V564RD ©2003 Silicon Storage Technology, Inc. 8051 CPU Core ALU, ACC, B-Register, Instruction Register, Program Counter, Timing and Control Flash Control Unit Watchdog Timer Block ...

Page 8

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 2.0 PIN ASSIGNMENTS (T2) P1.0 1 (T2 EX) P1.1 2 (ECI) P1.2 3 (CEX0) P1.3 4 (CEX1 / SS#) P1.4 5 (CEX2 / MOSI) P1.5 6 (CEX3 / MISO) P1.6 7 40-pin PDIP (CEX4 / SCK) P1.7 8 Top View RST 9 (RXD) P3.0 10 (TXD) P3.1 11 (INT0#) P3.2 12 (INT1#) P3.3 13 (T0) P3.4 14 (T1) P3.5 15 (WR#) P3.6 16 (RD#) P3.7 17 XTAL2 18 XTAL1 FIGURE 2- SSIGNMENTS FOR (CEX2 / MOSI) P1 ...

Page 9

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 2.1 Pin Descriptions TABLE 2- ESCRIPTIONS 1 Symbol Type Name and Functions P0[7:0] I/O Port 0: Port 8-bit open drain bi-directional I/O port output port each pin can sink several LS TTL inputs. Port 0 pins that have ‘1’s written to them float, and in this state can be used as high-impedance inputs ...

Page 10

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE 2- ESCRIPTIONS 1 Symbol Type Name and Functions P3[2] I INT0#: External Interrupt 0 Input P3[3] I INT1#: External Interrupt 1 Input P3[4] I T0: External count input to Timer/Counter 0 P3[5] I T1: External count input to Timer/Counter 1 P3[6] O WR#: External Data Memory Write strobe P3[7] O RD#: External Data Memory Read strobe ...

Page 11

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 3.0 MEMORY ORGANIZATION The device has separate address spaces for program and data memory. 3.1 Program Flash Memory There are two internal flash memory blocks in the device. The primary flash memory block (Block 0) has 64/32 KByte. The secondary flash memory block (Block 1) has 8 KByte ...

Page 12

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet EA FFFFH FFFFH E000H DFFFH External 8000H 64 KByte 7FFFH 2000H 1FFFH 0000H 0000H FIGURE 3- ROGRAM EMORY 3.2 Program Memory Block Switching The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block used for the lowest 8 KByte of the program address space ...

Page 13

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 3.2.1 Reset Configuration of Program Memory Block Switching Program memory block switching is initialized after reset according to the state of the Start-up Configuration bit SC0 and/or SC1. The SC0 and SC1 bits are programmed via an external host mode command or an IAP Mode com- mand ...

Page 14

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet Expanded RAM Access (Indirect Addressing only): MOVX @DPTR DPTR contains 0A0H DPTR points to 0A0H and data in “A” is written to address 0A0H of the expanded RAM rather than external memory. Access to external memory higher than 2FFH using the ...

Page 15

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 2FFH Expanded RAM 768 Bytes (Indirect Addressing) 000H 2FFH Expanded RAM 000H FIGURE 3-3: I NTERNAL AND ©2003 Silicon Storage Technology, Inc. FFH (Indirect Addressing) Upper 128 Bytes Internal RAM 80H 7FH Lower 128 Bytes Internal RAM (Indirect & ...

Page 16

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 3.5 Dual Data Pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-4) ...

Page 17

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 3-7: CPU SFR RELATED Direct Symbol Description Address 1 ACC Accumulator E0H Register F0H 1 PSW Program Status D0H Word SP Stack Pointer 81H DPL Data Pointer 82H Low DPH Data Pointer 83H High 1 IE Interrupt Enable ...

Page 18

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE 3- ATCHDOG IMER Direct Symbol Description Address 1 WDTC Watchdog Timer C0H Control WDTD Watchdog Timer 85H Data/Reload 1. Bit Addressable SFRs TABLE 3-10 SFR IMER OUNTERS Direct Symbol Description Address TMOD Timer/Counter 89H Mode Control ...

Page 19

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 3-11: I SFR NTERFACE S Direct Symbol Description Address SBUF Serial Data Buffer 99H 1 SCON Serial Port Control 98H SADDR Slave Address A9H SADEN Slave Address B9H Mask SPCR SPI Control D5H Register SPSR SPI Status AAH ...

Page 20

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet SuperFlash Configuration Register (SFCF) Location 7 6 B1H - IAPEN Symbol Function IAPEN Enable IAP operation 0: IAP commands are disabled 1: IAP commands are enabled SWR Software Reset See Section 10.2, “Software Reset” BSEL Program memory block switching bit See Figure 3-1, Figure 3-2, Table 3-3, and Table 3-4 ...

Page 21

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC SuperFlash Data Register (SFDT) Location 7 6 B5H Symbol Function SFDT Mailbox register for interfacing with flash memory block. (Data register). SuperFlash Status Register (SFST) (Read Only Register) Location 7 6 B6H SB1_i SB2_i Symbol Function SB1 ...

Page 22

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet Interrupt Enable (IE) Location 7 6 A8H EA EC Symbol Function EA Global Interrupt Enable Disable 1 = Enable EC PCA Interrupt Enable. ET2 Timer 2 Interrupt Enable. ES Serial Interrupt Enable. ET1 Timer 1 Interrupt Enable. EX1 External 1 Interrupt Enable. ET0 Timer 0 Interrupt Enable. ...

Page 23

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Interrupt Priority (IP) Location 7 6 B8H - PPC Symbol Function PPC PCA interrupt priority bit. PT2 Timer 2 interrupt priority bit. PS Serial Port interrupt priority bit. PT1 Timer 1 interrupt priority bit. PX1 External interrupt 1 priority bit. PT0 Timer 0 interrupt priority bit. ...

Page 24

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet Auxiliary Register (AUXR) Location 7 6 8EH - - Symbol Function EXTRAM Internal/External RAM access 0: Internal Expanded RAM access within range of 00H to 2FFH using MOVX @Ri / @DPTR. Beyond 300H, the MCU always accesses external data memory. For details, refer to Section 3.4, “Expanded Data RAM Addressing” . ...

Page 25

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Watchdog Timer Data/Reload Register (WDTD) Location 7 6 85H Symbol Function WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set. PCA Timer/Counter Control Register Location 7 6 D8H Bit addressable Symbol Function ...

Page 26

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet PCA Timer/Counter Mode Register Location 7 6 D9H CIDL WDTE 1. Not bit addressable Symbol Function CIDL Counter Idle Control: 0: Programs the PCA Counter to continue functioning during idle mode 1: Programs the PCA Counter to be gated off during idle ...

Page 27

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC PCA Compare/Capture Module Mode Register Location 7 6 DAH - ECOM0 DBH - ECOM1 DCH - ECOM2 DDH - ECOM3 DEH - ECOM4 1. Not bit addressable Symbol Function - Not implemented, reserved for future use. Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate. ...

Page 28

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet SPI Control Register (SPCR) Location 7 6 D5H SPIE SPE Symbol Function SPIE If both SPIE and ES are set to one, SPI interrupts are enabled. SPE SPI enable bit. 0: Disables SPI. 1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7. ...

Page 29

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC SPI Data Register (SPDR) Location 7 6 86H Power Control Register (PCON) Location 7 6 87H SMOD1 SMOD0 Symbol Function SMOD1 Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. ...

Page 30

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet Serial Port Control Register (SCON) Location 7 6 98H SM0/FE SM1 Symbol Function FE Set SMOD0 = 1 to access FE bit framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software. ...

Page 31

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Timer/Counter 2 Control Register (T2CON) Location 7 6 C8H TF2 EXF2 Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1 ...

Page 32

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 4.0 FLASH MEMORY PROGRAMMING The device internal flash memory can be programmed or erased using the following two methods: • External Host Programming mode • In-Application Programming (IAP) mode 4.1 External Host Programming Mode External host programming mode allows the user to pro- gram the flash memory directly without using the CPU ...

Page 33

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 4- XTERNAL OST Operation RST PSEN# Read- IH1 IL Chip-Erase V V IH1 IL Block-Erase V V IH1 IL Sector-Erase V V IH1 IL Byte-Program V V IH1 IL Byte-Verify (Read IH1 IL Prog-SC0 V V IH1 IL Prog-SC1 V V IH1 IL Prog-SB1 V V IH1 ...

Page 34

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 4.1.1 Product Identification The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms. The Read-ID com- mand is selected by the command code P3[7:6] and P2[7:6] ...

Page 35

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC The Prog-SB1, Prog-SB2, Prog-SB3 commands program the security bits, the functions of these bits are described in the Security Lock section and also in Table 9-1. Once pro- grammed, these bits can only be erased through a Chip- Erase command. See Figure 13-21 for timing waveforms. ...

Page 36

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE 4- DDITIONAL EAD Address 60H X 61H Don’t care 4.2 In-Application Programming Mode The device offers either KByte of in-application programmable flash memory. During in-application pro- gramming, the CPU of the microcontroller enters IAP mode. The two blocks of flash memory allow the CPU to execute user code from one block, while the other is being erased or reprogrammed concurrently ...

Page 37

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 4.2.4 In-Application Programming Mode Commands All of the following commands can only be initiated in the IAP mode. In all situations, writing the control byte to the SFCM register will initiate all of the operations. All com- mands will not be enabled if the security locks are enabled on the selected memory block ...

Page 38

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 4.2.4.4 Byte-Program The Byte-Program command programs data into a single byte. The address is determined by the contents of SFAH and SFAL. The data byte is in SFDT. IAP Enable ORL SFCF, #40H Program byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL ...

Page 39

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 4.2.4.7 Prog-SC0, Prog-SC1 Prog-SC0 command is used to program the SC0 bit. This command only changes the SC0 bit and has no effect on BSEL bit until after a reset cycle. SC0 bit previously in un-programmed state can be pro- grammed by this command. The Prog-SC0 command should reside only in Block 1 or external code memory ...

Page 40

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 1 TABLE 4-6: IAP C OMMANDS FOR Operation SFCM [6:0] 3 Chip-Erase 5 Block-Erase 5 Sector-Erase 5 Byte-Program 5 Byte-Verify (Read) 9 Prog-SB1 9 Prog-SB2 9 Prog-SB3 9 Prog-SC0 9 Enable-Clock-Double 1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands. 2. Interrupt/Polling enable for flash operation completion SFCM[7] =1: Interrupt enable for flash operation completion 0: polling enable for flash operation completion 3 ...

Page 41

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 5.0 TIMERS/COUNTERS 5.1 Timers The device has three 16-bit registers that can be used as either timers or event counters. The three timers/counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of 8-bit registers in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte ...

Page 42

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 5.3 Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed input the external clock for Timer/Counter output a 50% duty cycle clock ranging from 122 MHz MHz operating frequency ( MHz in 12 clock mode) ...

Page 43

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC RXD D0 Start bit RI SMOD0=X FE SMOD0=1 FIGURE 6-2: UART T IMINGS IN RXD D0 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 FIGURE 6-3: UART T IMINGS IN ©2003 Silicon Storage Technology, Inc Data byte M 1 ODE Data byte ODES AND ...

Page 44

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 6.1.2 Automatic Address Recognition Automatic Address Recognition helps to reduce the MCU time and power required to talk to multiple serial devices. Each device is hooked together sharing the same serial link with its own address. In this configuration, a device is only interrupted when it receives its own address, thus eliminating the software overhead to compare addresses ...

Page 45

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Select Slave 3 Only Slave 2 Given Address Possible Addresses 1111 X0X1 The user could use the possible addresses above to select slave 3 only. Another combination could be to select slave 2 and 3 only as shown below. Select Slaves 2 & 3 Only Slaves 2 & ...

Page 46

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 6.2.3 SPI Transfer Formats SCK Cycle # (for reference) SCK (CPOL=0) SCK (CPOL=1) MOSI MSB (from Master) MISO MSB (from Slave) SS# (to Slave) FIGURE 6-5: SPI T RANSFER SCK Cycle # (for reference) SCK (CPOL=0) SCK (CPOL=1) MOSI MSB (from Master) ...

Page 47

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 7.0 WATCHDOG TIMER The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and auto- matic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period ...

Page 48

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 8.0 PROGRAMMABLE COUNTER ARRAY The Programmable Counter Array (PCA) present on the SST89E/V554RC and SST89E/V564RD is a special 16-bit timer that has five 16-bit capture/compare modules. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator ...

Page 49

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC The table below summarizes various clock inputs at two common frequencies. TABLE 8-2: PCA T /C IMER OUNTER PCA Timer/Counter Mode Mode 0: f /12 OSC Mode 1: 1 Mode 2: Timer 0 Overflows Timer 0 programmed in: 8-bit mode 16-bit mode 8-bit auto-reload Mode 3: External Input MAX 1. In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled. CMOD’ ...

Page 50

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 8.3 Compare/Capture Modules Each PCA module has an associated SFR with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. Refer to “PCA Compare/Capture Module Mode Reg- ister (CCAPMn)” on page 27 for details. The registers each contain 7 bits which are used to control the mode each module will operate in ...

Page 51

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 8-5: PCA M M ODULE ODES Without Interrupt enabled ECOMy CAPPy CAPNy MATy - User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate. ...

Page 52

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 8.3.1 Capture Mode Capture mode is used to capture the PCA timer/counter value into a module’s capture registers (CCAPnH and CCAPnL). The capture will occur on a positive edge, nega- tive edge, or both on the corresponding module’s pin. To use one of the PCA modules in the capture mode, either one or both the CCAPM bits CAPN and CAPP for that module must be set ...

Page 53

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 8.3.2 16-Bit Software Timer Mode The 16-bit software timer mode is used to trigger interrupt routines, which must occur at periodic intervals setup by setting both the ECOM and MAT bits in the module’s CCAPMn register. The PCA timer will be compared to the module’ ...

Page 54

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 8.3.3 High Speed Output Mode The high speed output mode is used to toggle a port pin when a match occurs between the PCA timer and the pre- loaded value in the compare registers. In this mode, the CEX output pin (on port 1) associated with the PCA mod- ...

Page 55

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 8.3.4 Pulse Width Modulator The Pulse Width Modulator (PWM) mode is used to gener- ate 8-bit PWMs by comparing the low byte of the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the output is low. When CL ≥ ...

Page 56

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 8.3.5 Watchdog Timer The Watchdog Timer mode is used to improve reliability in the system without increasing chip count (See Figure 8-6). Watchdog Timers are useful for systems that are suscepti- ble to noise, power glitches, or electrostatic discharge. It can also be used to prevent a software deadlock. If during the execution of the user’ ...

Page 57

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 9.0 SECURITY LOCK The security lock protects against software piracy and pre- vents the contents of the flash from being read by unautho- rized parties. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. There are two different types of security locks in the device security lock system: hard lock and SoftLock ...

Page 58

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE 9- ECURITY OCK PTIONS Security Lock Bits Level SFST[7:5] SB1 1 000 U 2 100 P 3 011 U 101 P 010 U 110 P 001 U 4 111 Programmed (Bit logic state = 0 Unprogrammed (Bit logic state = 1). 2. SFST[7:5] = Security Lock Status Bits (SB1_i, SB2_i, SB3_i) 9 ...

Page 59

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 9- ECURITY OCK CCESS Level SFST[7:5] 111b 4 (hard lock on both blocks) 011b/101b (hard lock on both blocks) 001b/110b (Block 0 = SoftLock, Block 1 = hard lock) 3 010b (SoftLock on both blocks) 100b 2 (SoftLock on both blocks) 000b 1 (unlock) 1. Location of MOVC or IAP instruction 2 ...

Page 60

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 10.0 RESET A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable ...

Page 61

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 10.4 Interrupt Priority and Polling Sequence The device supports eight interrupt sources under a four level priority scheme. Table 10-1 summarizes the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt vector ...

Page 62

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 0 INT0# IT0 1 Brown-out TF0 0 INT1# IT1 1 TF1 ECF CF CCFn ECCFn RI TI SPIF SPIE TF2 EXF2 Individual FIGURE 10- NTERRUPT TRUCTURE ©2003 Silicon Storage Technology, Inc. IP/IPH/IPA/IPAH IE & IEA Registers Registers IE0 IE1 Global Disable Enables ...

Page 63

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 11.0 POWER-SAVING MODES The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are idle and power-down, see Table 11-1. 11.1 Idle Mode Idle mode is entered setting the IDL bit in the PCON regis- ter ...

Page 64

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 12.0 SYSTEM CLOCK AND CLOCK OPTIONS 12.1 Clock Input Options and Recom- mended Capacitor Values for Oscillator Shown in Figure 12-1 are the input and output of an inter- nal inverting amplifier (XTAL1, XTAL2), which can be con- figured for use as an on-chip oscillator. ...

Page 65

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 13.0 ELECTRICAL SPECIFICATION Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...

Page 66

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE 13- ONDITIONS OF Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . C See Figures 13-8 and 13-10 TABLE 13- ECOMMENDED YSTEM Symbol Parameter 1 T Power-up to Read Operation PU-READ 1 T Power-up to Write Operation PU-WRITE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter ...

Page 67

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 13.1 DC Electrical Characteristics TABLE 13- LECTRICAL HARACTERISTICS FOR T = -40°C +85° Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Input High Voltage (XTAL1, RST) IH1 V Output Low Voltage (Ports 1.5, 1.6, 1. Output Low Voltage (Ports ...

Page 68

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 1. Under steady state (non-transient) conditions, I Maximum I per port pin: 15mA OL Maximum I per 8-bit port:26mA OL Maximum I total for all outputs:71mA exceeds the test condition Pins are not guaranteed to sink current greater than the listed test conditions. ...

Page 69

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 13- LECTRICAL HARACTERISTICS FOR T = -40°C +85° Symbol Parameter I Power Supply Current DD IAP Mode @ 12 MHz @ 33 MHz Active Mode @ 12 MHz @ 33 MHz Idle Mode @ 12 MHz @ 33 MHz Power-down Mode (min Under steady state (non-transient) conditions, I ...

Page 70

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet FIGURE 13- REQUENCY FIGURE 13- REQUENCY DD ©2003 Silicon Storage Technology, Inc. Maximum Active I DD Maximum Idle I Typical Active I DD Typical Idle Internal Clock Frequency (MHz) ...

Page 71

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 13.2 AC Electrical Characteristics AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 13- LECTRICAL HARACTERISTICS T = -40°C +85° Symbol Parameter 1/T x1 Mode Oscillator Frequency CLCL ...

Page 72

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TABLE 13- LECTRICAL HARACTERISTICS T = -40°C +85° Symbol Parameter T Data Valid to WR# High to Low QVWX Transition T Data Hold After WR# WHQX T Data Valid to WR# High QVWH T RD# Low to Address Float RLAZ T RD# to WR# High to ALE High WHLH 1 ...

Page 73

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC T LHLL ALE T AVLL PSEN# PORT 0 PORT 2 FIGURE 13- XTERNAL ROGRAM T LHLL ALE PSEN# RD# T AVLL A0-A7 FROM RI or DPL PORT 0 PORT 2 FIGURE 13- XTERNAL ATA ©2003 Silicon Storage Technology, Inc. T LLIV T LLPL T PLIV T PLAZ T PXIZ T LLAX ...

Page 74

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet T LHLL ALE PSEN# WR# T AVLL PORT 0 A0-A7 FROM RI or DPL PORT 2 FIGURE 13- XTERNAL ATA TABLE 13- XTERNAL LOCK Symbol Parameter 1/T Oscillator Frequency CLCL T CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL ...

Page 75

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 13-10 ERIAL ORT IMING Symbol Parameter T Serial Port Clock Cycle Time XLXL T Output Data Setup to Clock Rising Edge QVXH T Output Data Hold After Clock Rising Edge XHQX T Input Data Hold After Clock Rising Edge ...

Page 76

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet TO DUT FIGURE 13-10 EST OAD RST EA# XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS All other pins disconnected FIGURE 13-11 EST ONDITION CTIVE ODE RST EA# 89x564 (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS All other pins disconnected ...

Page 77

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TABLE 13-11 XTERNAL ODE 2,3 Parameter Reset Setup Time Read-ID Command Width PSEN# Setup Time Address, Command, Data Setup Time Chip-Erase Time Block-Erase Time Sector-Erase Time Program Setup Time Address, Command, Data Hold 4 Byte-Program Time Select-Block Program Time ...

Page 78

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 13.3 Flash Memory Programming Timing Diagrams with External Host Mode RST PSEN# ALE/PROG# EA# P2[7:6] ,P3[7:6] P3[5:4] ,P2[5:0] ,P1 P0 Device ID = 91H for SST89E564RD FIGURE 13-14: R -ID EAD Reads chip signature and identification registers at the addressed location RST PSEN# ALE/PROG# EA# P3[3] P3[5:4], P2[5:0] P3[7:6], P2[7:6] FIGURE 13-15 ELECT ...

Page 79

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC T SU RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] FIGURE 13-16 HIP RASE Erases both flash memory blocks. Security lock is ignored and the security bits are erased too RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] FIGURE 13-17 LOCK RASE FOR Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. ...

Page 80

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet T SU RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] P3[5:4], P2[5:0] FIGURE 13-18 LOCK RASE FOR Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] P3[5:4], P2[5:0] P1 FIGURE 13-19 ECTOR RASE Erases the addressed sector if the security lock is not activated on that flash memory block. ...

Page 81

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC T SU RST PSEN# ALE/PROG# EA# P3[3] P3[5:4], P2[5: P3[7:6], P2[7:6] FIGURE 13-20 YTE ROGRAM Programs the addressed code byte if the byte location has been successfully erased and not yet programmed. Byte-Program operation is only allowed when the security lock is not activated on that flash memory block. ...

Page 82

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet T SU RST PSEN# ALE/PROG# EA# P3[3] P3[5:4], P2[5:0] P3[7:6], P2[7:6] FIGURE 13-22: P -SC0 / P ROG ROG Programs the start-up configuration bit SC0/SC1. Only a Chip-Erase will erase a programmed SC0/SC1 bit. Prog-SC1 applies to SST89E554RC/SST89V554RC only RST PSEN# ALE/PROG# EA# P3[7:6], P2[7: P3[5:4], P2[5:0] FIGURE 13-23 YTE ERIFY Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. © ...

Page 83

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC 14.0 PRODUCT ORDERING INFORMATION Device Speed Suffix1 SST89x5x4xx - XX - 14.1 Valid Combinations Valid combinations for SST89E564RD SST89E564RD-40-C-PI SST89E564RD-40-C-NJ SST89E564RD-40-I-PI SST89E564RD-40-I-NJ Valid combinations for SST89V564RD SST89V564RD-33-C-PI SST89V564RD-33-C-NJ SST89V564RD-33-I-PI SST89V564RD-33-I-NJ Valid combinations for SST89E554RC SST89E554RC-40-C-PI SST89E554RC-40-C-NJ SST89E554RC-40-I-PI SST89E554RC-40-I-NJ Valid combinations for SST89V554RC ...

Page 84

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet 15.0 PACKAGING DIAGRAMS 40 1 Pin #1 Identifier .065 .075 Base Plane Seating Plane .015 Min. .063 .045 .090 .055 Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .115; SST min is less stringent 2 ...

Page 85

... FlashFlex51 MCU SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC TOP VIEW .685 .695 Optional .646 † Pin #1 Identifier .656 .042 .048 1 44 .042 .048 † .685 .646 .695 .656 .050 BSC. Note: 1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. ...

Page 86

... SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC Data Sheet Pin #1 Identifier 10.00 ± 0.10 12.00 ± 0.25 1.2 max. Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±0.05) mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm. ...

Related keywords

SST89V564RD-33-I-PJ datasheet
SST89V564RD-33-I-PJ data sheet
SST89V564RD-33-I-PJ pdf datasheet
SST89V564RD-33-I-PJ component
SST89V564RD-33-I-PJ part
SST89V564RD-33-I-PJ distributor
SST89V564RD-33-I-PJ RoHS
SST89V564RD-33-I-PJ datasheet download