SST89V564RD-33-I-PJ SST [Silicon Storage Technology, Inc], SST89V564RD-33-I-PJ Datasheet - Page 60

• Manufacturer Part Number: SST89V564RD-33-I-PJ
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
10.0 RESET
A system reset initializes the MCU and begins program
execution at program memory location 0000H. The reset
input for the device is the RST pin. In order to reset the
device, a logic level high must be applied to the RST pin for
at least two machine cycles (24 clocks), after the oscillator
becomes stable. ALE, PSEN# are weakly pulled high dur-
ing reset. During reset, ALE and PSEN# output a high level
in order to perform a proper reset. This level must not be
affected by external element. A system reset will not affect
the 1 KByte of on-chip RAM while the device is running,
however, the contents of the on-chip RAM during power up
are indeterminate. Following reset, all Special Function
Registers (SFR) return to their reset values outlined in
Tables 3-7 to 3-11.
10.1 Power-on Reset
At initial power up, the port pins will be in a random state
until the oscillator has started and the internal reset algo-
rithm has weakly pulled all pins high. Powering up the
device without a valid reset could cause the MCU to
start executing instructions from an indeterminate
location. Such undefined states may inadvertently cor-
rupt the code in the flash.
When power is applied to the device, the RST pin must be
held high long enough for the oscillator to start up (usually
several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An exam-
ple of a method to extend the RST signal is to implement a
RC circuit by connecting the RST pin to V
µF capacitor and to V
shown in Figure 10-1. Note that if an RC circuit is being
used, provisions should be made to ensure the V
time does not exceed 1 millisecond and the oscillator start-
up time does not exceed 10 milliseconds.
For a low frequency oscillator with slow start-up time the
reset signal must be extended in order to account for the
slow start-up time. This method maintains the necessary
relationship between V
at an indeterminate location, which may cause corruption
in the code of the flash. The power-on detection is
designed to work as power up initially, before the voltage
reaches the brown-out detection level. The POF flag in the
PCON register is set to indicate an initial power up condi-
tion. The POF flag will remain active until cleared by soft-
ware. Please refer to Section 3.5, PCON register definition
for detail information.
For more information on system level design techniques,
please review the Design Considerations for the SST
FlashFlex51 Family Microcontroller application note.
©2003 Silicon Storage Technology, Inc.
DD
SS
and RST to avoid programming
through an 8.2KΩ resistor as
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
DD
through a 10
DD
rise
60
10.2 Software Reset
The software reset is executed by changing SFCF[1]
(SWR) from “0” to “1”. A software reset will reset the pro-
gram counter to address 0000H. All SFR registers will be
set to their reset values, except SFCF[1] (SWR), WDTC[2]
(WDTS), and RAM data will not be altered.
10.3 Brown-out Detection Reset
The device includes a brown-out detection circuit to protect
the system from severed supplied voltage V
SST89E564’s internal brown-out detection threshold is
3.85V, SST89V564’s brown-out detection threshold is
2.35V. For brown-out voltage parameters, please refer to
Tables 13-6 and 13-7.
When V
out detector triggers the circuit to generate a brown-out
interrupt but the CPU still runs until the supplied voltage
returns to the brown-out detection voltage V
default operation for a brown-out detection is to cause a
processor reset.
V
ods before the brown-out detection circuit will respond.
Brown-out interrupt can be enabled by setting the EBO bit
in IEA register (address E8H, bit 3). If EBO bit is set and a
brown-out condition occurs, a brown-out interrupt will be
generated to execute the program at location 004BH. It is
required that the EBO bit be cleared by software after the
brown-out interrupt is serviced. Clearing EBO bit when the
brown-out condition is active will properly reset the device.
If brown-out interrupt is not enabled, a brown-out condition
will reset the program to resume execution at location
0000H.
V
DD
DD
FIGURE 10-1: P
must stay below V
10µF
DD
8.2K
drops below this voltage threshold, the brown-
+
-
OWER
BOD
C
C
1
2
at least four oscillator clock peri-
-
ON
FlashFlex51 MCU
R
XTAL2
RST
XTAL1
ESET
SST89E/V564RD
SST89E/V554RC
S71207-04-000
C
IRCUIT
DD
fluctuations.
V
BOD
DD
1207 F20.1
. The
12/03