SST89V564RD-33-I-PJ SST [Silicon Storage Technology, Inc], SST89V564RD-33-I-PJ Datasheet - Page 55

• Manufacturer Part Number: SST89V564RD-33-I-PJ
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
8.3.4 Pulse Width Modulator
The Pulse Width Modulator (PWM) mode is used to gener-
ate 8-bit PWMs by comparing the low byte of the PCA
timer (CL) with the low byte of the compare register
(CCAPnL). When CL < CCAPnL the output is low. When
CL ≥ CCAPnL the output is high. To activate this mode, the
user must set the PWM and ECOM bits in the module’s
CCAPMn SFR. (See Figure 8-5 and Table 8-7)
In PWM mode, the frequency of the output depends on the
source for the PCA timer. Since there is only one set of CH
and CL registers, all modules share the PCA timer and fre-
quency. Duty cycle of the output is controlled by the value
TABLE
©2003 Silicon Storage Technology, Inc.
PCA Timer Mode
1/12 Oscillator Frequency
1/4 Oscillator Frequency
Timer 0 Overflow:
External Input (Max)
FIGURE
8-bit
16-bit
8-bit Auto-Reload
8-7: P
8-5: PCA P
ULSE
ECOMn CAPPn CAPNn MATn
Enable
W
IDTH
Overflow
ULSE
M
0
ODULATOR
W
IDTH
PCA Timer/Counter
0
8-bit Comparator
M
ODULATOR
CCAPnH
CCAPnL
F
REQUENCIES
CL
0
3.9 KHz to 15.3 Hz
TOGn
M
0
ODE
11.8 KHz
3.9 KHz
5.9 KHz
12 MHz
15.5 Hz
0.06 Hz
55
PWMn ECCFn
loaded into the high byte (CCAPnH). Since writes to the
CCAPnH register are asynchronous, a new value written to
the high byte will not be shifted into CCAPnL for compari-
son until the next period of the output (when CL rolls over
from 255 to 00).
To calculate values for CCAPnH for any duty cycle, use
the following equation:
where CCAPnH is an 8-bit integer and Duty Cycle is a
fraction.
CL < CCAPnL
CL >= CCAPnL
0
PWM Frequency
CCAPnH = 256(1 - Duty Cycle)
CCAPMn
n=0 to 4
0
1
5.2 KHz to 20.3 Hz
15.6 KHz
5.2 KHz
7.8 KHz
16 MHz
20.3 Hz
0.08 Hz
1207 F38.2
S71207-04-000
CEXn
Data Sheet
T8-7.0 1207
12/03