SST89V564RD-33-I-PJ SST [Silicon Storage Technology, Inc], SST89V564RD-33-I-PJ Datasheet - Page 45

• Manufacturer Part Number: SST89V564RD-33-I-PJ
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
The user could use the possible addresses above to select
slave 3 only. Another combination could be to select slave 2
and 3 only as shown below.
More than one slave may have the same SADDR address
as well, and a given address could be used to modify the
address so that it is unique.
6.1.2.2 Using the Broadcast Address to Select Slaves
Using the broadcast address, the master can communicate
with all the slaves at once. It is formed by performing a logi-
cal OR of SADDR and SADEN with 0s in the result treated
as “don’t cares”.
“Don’t cares” allow for a wider range in defining the broad-
cast address, but in most cases, the broadcast address will
be FFH.
On reset, SADDR and SADEN are “0”. This produces an
given address of all “don’t cares” as well as a broadcast
address of all “don’t cares.” This effectively disables Auto-
matic Addressing mode and allows the microcontroller to
function as a standard 8051, which does not make use of
this feature.
©2003 Silicon Storage Technology, Inc.
Slave 2
Slaves 2 & 3
FIGURE
Given Address
1111 X0X1
6-4: SPI M
Slave 1
[phone] = SADEN
Select Slaves 2 & 3 Only
1111 1X11 = Broadcast
1111 0001 = SADDR
Select Slave 3 Only
Clock Generator
ASTER
Possible Addresses
SPI
-
Possible Addresses
SLAVE
1111 0011
MSB Master LSB
8-bit Shift Register
1111 1011
1111 1001
I
NTERCONNECTION
45
MISO MISO
MOSI MOSI
SCK
SS#
V DD
6.2 Serial Peripheral Interface
6.2.1 SPI Features
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6.2.2 SPI Description
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the SST89E/V564RD /
SST89E/V554RC and peripheral devices or between sev-
eral SST89E/V564RD / SST89E/V554RC devices.
Figure 6-4 shows the correspondence between master
and slave SPI devices. The SCK pin is the clock output and
input for the master and slave modes, respectively. The SPI
clock generator will start following a write to the master
devices SPI data register. The written data is then shifted
out of the MOSI pin on the master device into the MOSI pin
of the slave device. Following a complete transmission of
one byte of data, the SPI clock generator is stopped and
the SPIF flag is set. An SPI interrupt request will be gener-
ated if the SPI Interrupt Enable bit (SPIE) and the Serial
Port Interrupt Enable bit (ES) are both set.
An external master drives the Slave Select input pin, SS#/
P1[4], low to select the SPI module as a slave. If SS#/P1[4]
has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an
input port pin.
CPHA and CPOL control the phase and polarity of the SPI
clock. Figures 6-5 and 6-6 show the four possible combina-
tions of these two bits.
V SS
SCK
SS#
Master or slave operation
10 MHz bit frequency (max)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake up from idle mode (slave mode only)
MSB Slave LSB
8-bit Shift Register
1207 F15.1
S71207-04-000
Data Sheet
12/03