dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 176

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
14.1
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare x Control (OCxCON<2:0>)
register.
Output Compare modes.
output compare operation for various modes. The user
TABLE 14-1:
FIGURE 14-2:
DS70652E-page 176
OCM<2:0>
(OCM<2:0> = 110 or 111)
000
001
010
011
100
101
110
111
Continuous Pulse Mode
Active-High One-Shot
Active-Low One-Shot
Table 14-1
Output Compare Modes
(OCM<2:0> = 001)
(OCM<2:0> = 010)
(OCM<2:0> = 011)
(OCM<2:0> = 100)
(OCM<2:0> = 101)
Delayed One-Shot
Module Disabled
Active-Low One-Shot
Active-High One-Shot
Toggle Mode
Delayed One-Shot
Continuous Pulse
PWM Mode without Fault
Protection
PWM Mode with Fault
Protection
Toggle Mode
PWM Mode
OUTPUT COMPARE MODES
lists the different bit settings for the
TMRy
OUTPUT COMPARE OPERATION
Figure 14-2
Mode
OCxRS
OCxR
Output Compare
Mode Enabled
illustrates the
Controlled by GPIO register
Current output is maintained
0, if OCxR is zero
1, if OCxR is non-zero
0, if OCxR is zero
1, if OCxR is non-zero
OCx Pin Initial State
Timer is Reset on
0
1
0
0
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
Period Match
Note:
See Section 13. “Output Compare” in
the “dsPIC33F/PIC24H Family Reference
Manual”
OCxRS register restrictions.
OCx Rising Edge
OCx Falling Edge
OCx Rising and Falling Edge
OCx Falling Edge
OCx Falling Edge
No Interrupt
OCFA Falling Edge for OC1 to OC4
 2011-2012 Microchip Technology Inc.
OCx Interrupt Generation
(DS70209)
—
for
OCxR
and