dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 52

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

Visibility area (see
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.2
The
dsPIC33FJ32(GP/MC)101/102/104
separate 16-bit-wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps is shown in
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Program Memory Using Program Space
Microchip
dsPIC33FJ32(GP/MC)101/102/104 devices imple-
ment up to 2 Kbytes of data memory. Should an EA
point to a location outside of this area, an all-zero word
or byte will be returned.
4.2.1
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
To maintain backward compatibility with PIC
devices and improve data space memory usage
efficiency, the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104
supports both word and byte operations. As a
consequence of byte accessibility, all Effective Address
calculations are internally scaled to step through word-
aligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decoding
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
DS70652E-page 52
Data Address Space
DATA SPACE WIDTH
DATA MEMORY ORGANIZATION
AND ALIGNMENT
dsPIC33FJ16(GP/MC)101/102
dsPIC33FJ16(GP/MC)101/102
Section 4.6.3 “Reading Data from
Figure
4-4.
instruction
CPU
Visibility”).
has
®
MCU
and
and
set
a
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in progress is completed. If the error
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternately, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 core and peripheral modules for
controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.4
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV class of instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode with a working register
as an Address Pointer.
Note:
SFR SPACE
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout
information.
NEAR DATA SPACE
(SFRs).
 2011-2012 Microchip Technology Inc.
diagrams
These
are
for
used
device-specific
by
the