dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 38

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.3
The
dsPIC33FJ32(GP/MC)101/102/104 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
DS70652E-page 38
PSV and Table
Control Block
Data Access
Program Memory
Address Latch
Special MCU Features
Data Latch
23
dsPIC33FJ16(GP/MC)101/102
23
Controller
Interrupt
23
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
CPU CORE BLOCK DIAGRAM
to Various Blocks
Control Signals
Control
Decode and
Instruction
Stack
Logic
PCU
Program Counter
Control
24
8
PCH
Control
Logic
Loop
16
PCL
and
16
Y Data Bus
X Data Bus
Divide Support
DSP Engine
Instruction Reg
Data Latch
ROM Latch
Address Generator Units
Address
X RAM
Latch
16
16
The
dsPIC33FJ32(GP/MC)101/102/104 supports 16/16
and 32/16 divide operations, both fractional and
integer. All divide instructions are iterative operations.
They must be executed within a REPEAT loop, resulting
in a total execution time of 19 instruction cycles. The
divide operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
Data Latch
Address
Y RAM
Latch
EA MUX
W Register Array
16
16
16
dsPIC33FJ16(GP/MC)101/102
16 x 16
16
16-Bit ALU
 2011-2012 Microchip Technology Inc.
16
16
16
To Peripheral Modules
16
and