dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 255

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

22.1
REGISTER 22-1:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-0
Note 1:
CTMUEN
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
R/W-0
U-0
—
2:
CTMU Control Registers
If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more
information, see
The ADC module S&H capacitor is not automatically discharged between sample/conversion cycles.
Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor before
conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC must be
sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
Unimplemented: Read as ‘0’
U-0
U-0
—
—
CTMUCON1: CTMU CONTROL REGISTER 1
Section 10.4 “Peripheral Pin Select
W = Writable bit
‘1’ = Bit is set
CTMUSIDL
R/W-0
U-0
—
TGEN
R/W-0
U-0
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
EDGEN
R/W-0
U-0
—
(PPS)”.
EDGSEQEN
R/W-0
U-0
—
x = Bit is unknown
IDISSEN
R/W-0
U-0
—
DS70652E-page 255
(2)
CTTRIG
R/W-0
U-0
—
bit 8
bit 0