dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 98

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 7-2:
7.3
The
dsPIC33FJ32(GP/MC)101/102/104 devices implement
a total of 22 registers for the interrupt controller:
• INTCON1
• INTCON2
• IFSx
• IECx
• IPCx
• INTTREG
7.3.1
Global interrupt functions are controlled from INTCON1
and INTCON2. INTCON1 contains the Interrupt Nest-
ing Disable (NSTDIS) bit as well as the control and
status flags for the processor trap sources. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
DS70652E-page 98
Vector Number
Interrupt Control and Status
Registers
INTCON1 AND INTCON2
IFSx Registers
IECx Registers
dsPIC33FJ16(GP/MC)101/102
0
1
2
3
4
5
6
7
TRAP VECTORS
IVT Address
0x00000A
0x00000C
0x00000E
0x000006
0x000008
0x000010
0x000012
0x000004
and
7.3.4
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
7.3.5
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into Vector Number
(VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IPx
bits in the first positions of IPC0 (IPC0<2:0>).
7.3.6
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS Register, SR, contains the
• The CORCON register contains the IPL3 bit
All Interrupt registers are described in
through
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user
application can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
which, together with IPL<2:0>, also indicates the
current CPU Interrupt Priority Level. IPL3 is a
read-only bit so that trap events cannot be
masked by the user software.
AIVT Address
0x00010A
0x00010C
0x00010E
0x000104
0x000106
0x000108
0x000110
0x000112
Register 7-28
Table
IPCx Registers
INTTREG
STATUS/CONTROL REGISTERS
7-1. For example, the INT0 (External
 2011-2012 Microchip Technology Inc.
in the following pages.
Reserved
Oscillator Failure
Address Error
Stack Error
Math Error
Reserved
Reserved
Reserved
Trap Source
Register 7-1