dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 186

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 15-5:
DS70652E-page 186
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-8
bit 7
bit 6-4
bit 3
bit 2-0
Note 1:
U-0
U-0
—
—
2:
The PWMxCON1 register is a write-protected register. Refer to
Registers”
The Reset status for this bit depends on the setting of the PWMPIN Configuration bit (FPOR<7>):
• If PWMPIN = 1 (default), the PWM pins are controlled by the PORT register at Reset, meaning they
• If PWMPIN = 0, the PWM pins are controlled by the PWM module at Reset and are therefore, initially
are initially programmed as inputs (i.e., tri-stated).
programmed as output pins.
Unimplemented: Read as ‘0’
PMOD<3:1>: PWM I/O Pair Mode bits
1 = PWM I/O pin pair is in the Independent PWM Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
Unimplemented: Read as ‘0’
PEN3H:PEN1H: PWMxH I/O Enable bits
1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin is disabled, I/O pin becomes a general purpose I/O
Unimplemented: Read as ‘0’
PEN3L:PEN1L: PWMxL I/O Enable bits
1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin is disabled, I/O pin becomes a general purpose I/O
PEN3H
R/W-0
U-0
—
PWMxCON1: PWMx CONTROL REGISTER 1
for more information on the unlock sequence.
(2)
W = Writable bit
‘1’ = Bit is set
PEN2H
R/W-0
U-0
—
(2)
PEN1H
R/W-0
U-0
—
(2)
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
Section 15.3 “Write-Protected
(1)
PEN3L
PMOD3
R/W-0
R/W-0
 2011-2012 Microchip Technology Inc.
(2)
x = Bit is unknown
PEN2L
PMOD2
R/W-0
R/W-0
(2)
PEN1L
PMOD1
R/W-0
R/W-0
bit 8
bit 0
(2)