S9S12G96F0MLF Freescale Semiconductor, S9S12G96F0MLF Datasheet - Page 323

• Manufacturer Part Number: S9S12G96F0MLF
• Description: 16-bit Microcontrollers - MCU 16BIT 96K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G96F0MLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2).
8.3.2.7.3
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
Register
DBGXCTL control register.
Freescale Semiconductor
Address: 0x0027
SC[3:0]
SC[3:0]
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SC[3:0]
0000
Reset
Field
3–0
W
R
(DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug State Control Register 3 (DBGSCR3)
Figure 8-11. Debug State Control Register 3 (DBGSCR3)
= Unimplemented or Reserved
0
0
6
Table 8-20. State3 — Sequencer Next State Selection
Table 8-36
Table 8-18. State2 —Sequencer Next State Selection
Figure 8-1
Either Match0 or Match1 to Final State........Match2 to State3
Either Match0 or Match1 to Final State........Match2 to State1
MC9S12G Family Reference Manual, Rev.1.23
Table 8-19. DBGSCR3 Field Descriptions
Description (Unspecified matches have no effect)
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
0
0
5
and described in
Match2 to State1..... Match0 to Final State
Either Match0 or Match1 to Final State
Match2 to Final State
0
0
4
Match0 to State1
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Section 8.3.2.8.1, “Debug Comparator Control
SC3
0
3
SC2
0
2
S12S Debug Module (S12SDBGV2)
SC1
0
1
SC0
0
0
325