ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet
ATAES132-SH-ER
Specifications of ATAES132-SH-ER
Related parts for ATAES132-SH-ER
ATAES132-SH-ER Summary of contents
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... Access restrictions for the sixteen user zones are independently configured, which any key can be used with any zone. Keys can also be used for stand- alone authentication. This flexibility permits ATAES132 to be used in a wide range of applications. The Atmel AES-128 cryptographic engine operates in the AES-CCM mode to provide authentication, stored data encryption/decryption, and message authentication codes ...
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... The ATAES132 Secure Serial EEPROM architecture allows inserted into existing applications. The ATAES132 chip incorporates multiple physical security mechanisms to prevent release of the internally stored secrets. Secure personalization features are provided to facilitate third-party product manufacturing. Atmel ATAES132 Preliminary Datasheet 2 8760A− ...
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... User Zone Configuration ..................................................................................... 16 4.2. Key Configuration ............................................................................................... 17 4.3. VolatileKey Configuration ................................................................................... 19 4.4. Monontonic Counter Configuration ..................................................................... 20 5. Standard Serial EEPROM Read and Write Commands ................................. 21 5.2. Read ............................................................................................................. 21 5.3. Write ............................................................................................................. 22 6. Atmel ATAES132 Commands ......................................................................... 23 6.1. Command Block and Packet .............................................................................. 23 6.2. Command Summary ........................................................................................... 24 6.3. ReturnCode ........................................................................................................ 26 7. Command Definitions ...................................................................................... 27 7.1. Auth Command ................................................................................................... 27 7.2. AuthCheck Command ......................................................................................... 30 7.3. AuthCompute Command .................................................................................... 31 7.4. BlockRead Command ......................................................................................... 32 7 ...
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... C Interface ................................................................................ 122 Appendix K. SPI Interface ............................................................................... 131 Appendix L. Power Management .................................................................... 138 Appendix M. Block Checksum ......................................................................... 144 Appendix N. Atmel ATAES132 Command Response Time ............................ 146 Appendix O. Default Configuration .................................................................. 149 Appendix P. Serial Memory Backward Compatibility ...................................... 153 Appendix Q. Ordering Information ................................................................... 157 Appendix R. Errata .......................................................................................... 161 Appendix S. Revision History .......................................................................... 165 ...
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... The user memory can be accessed directly with the standard SPI or I read-only access. If the user zone security is activated, then the extended ATAES132 command set is used to access the contents of a user zone. The extended ATAES132 commands are executed by writing the command packet to the virtual ...
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... Byte Order The ATAES132 device uses a “big-endian” coding scheme and utilizes the same bit and byte orders as the standard Serial EEPROM. The byte order is identical to the NIST AES specifications (see Appendix A): • The most significant bit of each byte is transmitted first on the bus • ...
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... If the host begins a read operation in an open user zone, but continues reading until a prohibited section of memory is reached, the ATAES132 will continue to increment the address and will return 0xFF for each byte in the restricted user zone. If the host begins a read operation in an open user zone, but continues reading beyond the end of the user memory, the ATAES132 will return 0xFF for each byte requested but will stop incrementing the address ...
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... ATAES132 is processing a command or writing the EEPROM. When the ATAES132 is configured for I host can read the STATUS register only when the I If the ATAES132 is in the sleep or standby power state, reading the STATUS register forces the ATAES132 to wakeup; the STATUS register is 0xFF until the wakeup process is complete. ...
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... EEPROM contents and compares it to the data received from the host. If the data does not match the ATAES132 sets the EERR bit in the STATUS register and returns a DataMatch error code. If the data is correct, then the ReturnCode indicates success. ...
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... The SRAM is used to store the nonce and the random number generator (RNG) seed. The RNG seed is generated automatically by the ATAES132 as described in Section 3.6. The nonce is generated using the nonce command or the NonceCompute command. The nonce and RNG seed register are erased when the device loses power, enters the sleep state reset ...
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... Device Status Register (STATUS) The device status register is used for handshaking between the host microcontroller and the ATAES132. The host is expected to read the STATUS register before sending a command or reading a response. Reading the STATUS register does not alter the contents of the command memory buffer, the response memory buffer, or the value of the STATUS register. See Appendix G for the definition and behavior of the STATUS register ...
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... Changes to the I wakeup from the Sleep State. 2. The LockConfig, LockKeys, and LockSmall bytes can only be changed with the Lock command (See Section 7.19). Warning: The Atmel ATAES132 must always be locked by the customer prior to shipment to the end user to protect the customer secrets. (1) Write Never ...
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... A user zone can be configured to require an AES-CCM encryption for the EEPROM read or write operations. If encryption is required for write access, then the MAC is validated before the received (encrypted) data is written to the EEPROM. If encryption is required for read access, then the ATAES132 encrypts data when it is read from the internal EEPROM and generates an associated integrity MAC. ...
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... Limited Use Keys To prevent exhaustive attacks on the keys, the ATAES132 can be configured to limit the key usage with a monotonic counter key is configured with a usage counter, then the following steps are performed for any command using that key: Read the counter from memory to check if the count has reached the maximum count value 1 ...
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... ATAES132 SerialNum register value. The host must have a secure place to store the root secret to protect the integrity of the diversified keys. It may also be beneficial for the ATAES132 devices to contain secrets for validating the authenticity of the host. These secrets may need to be the same on all ATAES132 devices for a particular application to permit any client to validate any host. 3.6. Random Numbers The ATAES132 includes a high quality random number generator (RNG) for nonce generation, child key creation, and for the general random number generation ...
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... Most changes to the ZoneConfig registers take effect immediately. Changes to the AuthRead and EncRead bits do not affect the SPI Warning: The Atmel ATAES132 must always be locked by the customer prior to shipment to the end user to protect the customer secrets. See Section 7.19 for the lock command. (1)(2) Description ...
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... If 1b, then this key is permitted to be the target of a KeyImport command If 0b, then the KeyImport command is prohibited 5 If 1b, then the KeyExport and KeyCompute commands require prior authentication using the KeyID stored in LinkPointer If 0b, then prior authentication is not required Atmel ATAES132 Preliminary Datasheet (3) 17 8760A−CRYPTO−5/11 ...
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... Changes to the KeyConfig registers take effect immediately, which allows the functionality to be verified during the personalization process 2. Warning: The Atmel ATAES132 must always be locked by the customer prior to shipment to the end user to protect the customer secrets. See Section 7.19 for the lock command. 3. Warning: Since the encrypt command does not include an input MAC, the encrypt command can exhaustively be run with selected input data to attack the key ...
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... If 1b, then the WriteCompute command can be run using this key If 0b, then the WriteCompute command is prohibited 1 If 1b, then the DecRead command can be run using this key If 0b, then the DecRead command is prohibited Reserved for future use. All bits must be 0b. Atmel ATAES132 Preliminary Datasheet (1) 8760A−CRYPTO−5/11 19 ...
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... Changes to the CounterConfig registers take effect immediately, allowing the functionality to be verified during the personalization process 2. Warning: The Atmel ATAES132 must always be locked by the customer prior to shipment to the end user to protect the customer secrets. See Section 7.19 for the lock command. (1)(2) Bit ...
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... EEPROM page boundaries. 5.2.1. Read the Response Memory Buffer The host sends ATAES132 commands to the device by writing the command packet to the command memory buffer using a 2 standard SPI write command. The ATAES132 processes the command packet and places the response in the response memory buffer ...
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... Write the Key Memory or Configuration Memory The ATAES132 supports standard Serial EEPROM commands to write to the configuration memory or the key memory prior to locking. The ATAES132 is capable of writing bytes on a single physical page with each write operation. Note: Partial writes to key registers are prohibited If LockKeys has a value of 0x55 (unlocked) and the address points to key memory, then the starting address must be the first byte of a key register and 16 bytes of cleartext data must be sent ...
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... Command Block and Packet The host sends ATAES132 extended commands to the device in a block of at least nine bytes. The ATAES132 responses are returned to the host in a block of at least four bytes. Table 6-10. The command and response blocks are constructed in the following manner: ...
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... Encrypts data and generates the input MAC required to execute the EncWrite command Checks the output MAC and decrypts data which was encrypted by the EncRead command Encrypts a key for export to an ATAES132 device. Optionally generates the key being exported. Decrypts and writes a key which was output by the KeyExport command or KeyCompute ...
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... This command can also be used to write a host nonce directly into the Nonce register. 0x13 NonceCompute Generates a nonce in a manner which allows two ATAES132 devices to have identical nonce values 0x02 Random Returns a 128 bit random number from the internal random number generator ...
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... TempSenseErr Temperature sensor timeout error If ReturnCode has any value other than 0x00, no additional data will be returned by ATAES132. If the ReturnCode is greater than zero for any command that performs cryptographic operations, then the nonce will be invalidated. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 ...
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... Auth command, the AuthComplete status flag is set to NoAuth. If the InMAC is successfully verified in the inbound only or mutual authentication mode, then the AuthComplete status flag is set to YesAuth. The ATAES132 authentication status register only stores the result of the most recent authentication attempt. If there is a parsing or execution error then the prior authentication, status will be lost. ...
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... KeyLoad commands using the authenticated key are prohibited after authentication. (see Section 4.2) If 10b, then perform outbound only authentication If 01b, then perform inbound only authentication If 00b, then perform authentication reset Atmel ATAES132 Preliminary Datasheet 28 8760A−CRYPTO−5/11 ...
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... If an output MAC generation was required (and any optional input MAC verification succeeded), then a 16 byte MAC will be returned. The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 29 ...
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... The AuthCheck command is used to check the OutMAC generated by the Auth command or the counter command on a second ATAES132 device. This command can not check MACs created by other commands. To use this command the nonce must be identical on both devices (see Section 7.21.1) and the MacCount must have the same value ...
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... AuthCompute Command The AuthCompute command is used to compute a MAC which will be used to execute the Auth command or the counter command on a second ATAES132 device. To use this command, the nonce must be identical on both devices (see Section 7.21.1) and the MacCount must have the same value. Both devices must also contain identical key values, but it is not necessary for the KeyID on the origin device to match the KeyID on the destination device ...
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... The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Size (Bytes) Notes 1 0x10 1 Must be 0x00 2 The address of data to read 2 Upper byte is always 0x00. Lower byte is the number of bytes to read. Atmel ATAES132 Preliminary Datasheet 32 8760A−CRYPTO−5/11 ...
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... Bit 7: If 1b, include the first four bytes of the SmallZone in the MAC 2 Upper byte is always 0x00. Upper nibble of lower byte is always 0x0. Lower nibble of lower byte is the counter to be queried. 2 Always 0x0000 Integrity MAC for the counter increment operation Atmel ATAES132 Preliminary Datasheet InMAC OutMAC Prohibited Generated Prohibited No Required ...
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... The current value of the counter OutMac Integrity MAC for the counter read operation The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 34 ...
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... The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Size (Bytes) Notes 1 0x0B 1 Must be 0x00 2 Upper byte is always 0x00 Lower byte is the iteration count for the crunch engine 2 Always 0x0000 16 Input seed Atmel ATAES132 Preliminary Datasheet 35 8760A−CRYPTO−5/11 ...
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... DecRead Command The DecRead command is used to check the OutMAC generated by an EncRead command on a second ATAES132 device. If the MAC matches, then the bytes of data is returned to the host in the DecRead response. To use this command, the nonce must be identical on both devices (see Section 7.21.1) and the MacCount must have the same value ...
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... If these conditions are satisfied, then packets encrypted on the encrypt device can be decrypted on the decrypt device single ATAES132 will be used to encrypt packets for later decryption, then the same key value must be stored in two appropriately configured key registers to allow all of the requirements above to be satisfied. ...
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... Client decryption mode: The upper byte is the EMacCount. The lower byte is the number of bytes to be returned after decryption. (see Section 7.8.1) Integrity MAC for the input data Input data (ciphertext decrypted Atmel ATAES132 Preliminary Datasheet 38 8760A−CRYPTO−5/11 ...
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... KeyID 00 is always used to generate the key memory signature. The key memory signature generation mode is intended to be used during secure personalization of the ATAES132. The signature can be used to validate the contents of the key memory before locking the key memory. ...
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... ZoneConfig[UZ].ReadID key in the MAC Bit 6: If 1b, include the SerialNum in the MAC Bit 7: If 1b, include the first 4 bytes of the SmallZone in the MAC The address of data to be read Upper byte is always 0x00. Lower byte is the number of bytes to read. Atmel ATAES132 Preliminary Datasheet 40 8760A−CRYPTO−5/11 ...
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... The encrypt command accepts bytes of plaintext, encrypts the data and generates an integrity MAC. The encrypted data and OutMAC are returned to the system. The encrypt command can be used to encrypt packets for decryption by the same or by another ATAES132 if the requirements described in Section 7.8.1 are satisfied. ...
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... The input data must be encrypted with the current value of the key. If KeyConfig[WriteID].RandomNonce is 1b then nonce be random (See Section 7.20). • The input MAC must be generated with the current value of the key. The input MAC will be verified. See section 7.19 for the lock command. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 42 ...
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... Bit 7: If 1b, include the first four bytes of the SmallZone in the MAC The starting address of memory to be written Upper byte is always 0x00. Lower byte is the number of bytes to be written. Input MAC to be verified Encrypted Data (ciphertext) Atmel ATAES132 Preliminary Datasheet 43 8760A−CRYPTO−5/11 ...
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... ChipState = Power Up 0x5555 indicates the ChipState = "Wakeup from Sleep" See Section L.3 for a detailed description of ChipState Reserved for future use Size (Bytes) Notes 1 0x0C 1 Must be 0x00 2 Selects the register to read 2 Always 0x0000 0 Atmel ATAES132 Preliminary Datasheet 44 8760A−CRYPTO−5/11 ...
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... Table 7-45. DeviceNum coding for INFO response and DeviceNum in the configuration memory register Description Early pre-production samples Pre-production samples INFO DeviceNum DeviceNum Register 0x0A02 0x0A 0x0A04 0x0A Atmel ATAES132 Preliminary Datasheet 45 8760A−CRYPTO−5/11 ...
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... KeyCompute, KeyExport, nonce, and random commands. The RNG seed register is subject to the same write endurance limitations as the other bytes in the EEPROM (see Section 9.2 for the EEPROM specifications) – the application developer must not exceed the write endurance limit. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 46 ...
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... Bit 7: If 1b, include the first four bytes of the SmallZone in the MAC Upper byte is always 0x00. Lower byte is the ChildKeyID for key memory loads or the ParentKeyID for VolatileKey loads Usage restrictions for VolatileKey if mode bit (see Section 4.3) Optional input MAC (see above) Atmel ATAES132 Preliminary Datasheet 47 8760A−CRYPTO−5/11 ...
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... KeyExport Command The KeyExport command is used to encrypt a key for export to a second ATAES132 device. The source of the key can be the internal random number generator, the VolatileKey register, or external data. The resulting encrypted key is used as the input to the KeyImport command or KeyLoad command. This command does not modify the stored keys. ...
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... If mode bits 5, 6, and 7 are 0b, then this field must be present, but is ignored. If mode bits 2 and 3 are 01b, then this field contains the key (plaintext encrypted. For all other cases this field is ignored. Atmel ATAES132 Preliminary Datasheet (1) 49 8760A−CRYPTO−5/11 ...
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... Section 6.3 OutMac 16 Integrity MAC for the encrypted key OutData 16 Encrypted key (ciphertext) The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 50 ...
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... SmallZone register in the SecondBlock field must match the values on the origin device. The ManufacturingID register must be identical on both devices, since it is always included in the MAC calculation. A valid nonce is required to run the KeyImport command. If the KeyConfig[KeyID].RandomNonce bit is 1b for the decrypt key, then the nonce must be random. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 51 ...
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... The value of this field must match the second authenticate-only block used when executing the KeyCompute command or KeyExport command on the origin device. If Mode bits 5, 6, and 7 are 0b, then this field must be present, but is ignored MAC for the encrypted key Input key (ciphertext decrypted Atmel ATAES132 Preliminary Datasheet 52 8760A−CRYPTO−5/11 ...
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... Upper byte is always 0x00. Lower byte is the ChildKeyID for the key memory loads or the ParentKeyID for VolatileKey loads. 2 Usage restrictions for VolatileKey if mode bit (See Section 4.3) 16 Integrity MAC for the input data 16 Encrypted key value (ciphertext) Atmel ATAES132 Preliminary Datasheet 53 8760A−CRYPTO−5/11 ...
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... Must be 0x00 2 Upper byte is always 0x00. Lower byte is the location where the key will be stored. Legal values: 0x00 to 0x0F (standard keys), 0xFF (volatile key). 2 Starting address of the key data structure in user memory Atmel ATAES132 Preliminary Datasheet ...
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... The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Size (Bytes) Notes 1 0x0F 1 Must be 0x00 2 Upper byte is always 0x00 Lower byte is the KeyID for the AES key 2 Always 0x0000 16 Input to the AES block (plaintext) Atmel ATAES132 Preliminary Datasheet 55 8760A−CRYPTO−5/11 ...
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... ZoneConfig[Zone].WriteID, otherwise, the MAC is ignored. The lock command changes the ZoneConfig[Zone].ReadOnly byte from 0x55 (read/write) to 0x00 when the ReadOnly feature is activated not possible to change a read-only User Zone to read/write after Configuration Memory is locked. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 56 ...
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... If mode bit 2 is 1b, contains the CRC-16 checksum generated of the memory segment being locked. If mode bit 2 is 0b, this parameter must be 0x0000. If Mode[0:1] is 11b, contains the MAC authorizing update of ZoneConfig[Zone].ReadOnly as described in Section 7.19.2. For all other modes this field is ignored. Atmel ATAES132 Preliminary Datasheet 57 8760A−CRYPTO−5/11 ...
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... The nonce command generates and/or stores a 96 bit nonce in the SRAM nonce register for use by subsequent cryptographic commands not necessary to generate a new nonce before each cryptographic operation because the ATAES132 includes the MacCount in the MAC calculations (see Section I.1) to guarantee uniqueness. ...
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... If 0b, use the InSeed as the nonce (Inbound nonce mode), mode bit 1 is ignored Bit 1: If 0b, update the EEPROM RNG seed prior to nonce generation If 1b, generate a random nonce using the existing RNG seed Bits 2-7: Reserved. Must be 0b Always 0x0000 Always 0x0000 Input seed (required) Atmel ATAES132 Preliminary Datasheet (1) 59 8760A−CRYPTO−5/11 ...
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... Nonce Synchronization The following procedure synchronizes the nonce and the MacCount on two ATAES132 devices. In this procedure, the device where the procedure begins is referred to as “A” and the device it is synchronized with is referred to as “B”. The random command is executed on Device A with mode bit 2 set to 1b. The first 12 bytes of the random field 1 ...
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... Upon success, 0x00 will be returned. Any command execution failure or validation failure generates a non-zero error code, per Section 6.3. The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 61 ...
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... Bit 2: If 0b, then return the random number. Do not change the nonce. If 1b, then store the first 12 bytes of the random number in the nonce register and return the 16 byte random number Bits Reserved. Must Always 0x0000 2 Always 0x0000 0 Atmel ATAES132 Preliminary Datasheet 62 8760A−CRYPTO−5/11 ...
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... Upon success, 0x00 will be returned. Any command execution failure or validation failure generates a non-zero error code, per Section 6.3. Random 16 The random number The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum. This block format is described in Section 6.1. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 63 ...
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... I C device address. The ATAES132 will answer the ACK poll with an I reset. The ACK poll reply will change to ACK when the device is in the active state. The ATAES132 will not accept any I commands while it is "busy". ACK polling is described in Section J.3.8. ...
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... A device in the standby state will retain all volatile memory contents. A device in the standby state does not go thru a power up sequence upon wakeup. The ATAES132 exits the sleep or standby state if a wakeup event occurs on the IO pins. Wakeup is discussed in Section L.2. See Appendix L for a detailed description of the ATAES132 sleep, standby, wakeup, and power management functions. ...
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... The T value is stored in the first two bytes of the TempOffset register in the configuration memory. (see Section E.2.18) OFFSET The ATAES132 devices with a calibrated temperature sensor are available at additional cost. Contact Atmel for the die temperature formula for calibrated temperature sensors. Table 7-71. Input parameters ...
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... The value of this field must match the second authenticate-only block to be used when executing the EncWrite command on the destination device. If mode bits 5, 6, and 7 are 0b, then this field must be present, but is ignored Input data to be encrypted (plaintext) Atmel ATAES132 Preliminary Datasheet 67 8760A−CRYPTO−5/11 ...
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... I C mode not used 2 C mode not used or AuthO out 2 C mode serial data I serial communication modes this pin is used as the serial interface clock. Atmel ATAES132 Preliminary Datasheet Type Input Output N.C. Ground Input / Output Input N.C. Power communication ...
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... DC output current ......................................... 5.0mA Voltage on any pin .................. -0. HBM ESD ...................................... 2000V minimum 9.2. Reliability The ATAES132 is fabricated with the Atmel high reliability CMOS EEPROM manufacturing technology. The reliability ratings in Table 9-1 apply to each byte of the EEPROM memory. Table 9-76. EEPROM Reliability Parameter Write endurance (each byte) Data retention (at 55° ...
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... SPI interface mode, fmax is 10 MHz. 5. See Appendix L for sleep and standby state information. The sleep command is described in Section 7.24. 6. The ATAES132 does not support hot swapping or hot plugging. Connecting or disconnecting this device to a system while power is energized can cause permanent damage to the ATAES132. ...
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... C interface mode, if Auth signaling is enabled, the SO pin functions as the AuthO output. (See Section J.5) When AuthO is high, the V impedance state – the V All values are preliminary and will be updated after characterization. 9.4. AC Characteristics Table 9-79. AC characteristics of the Atmel ATAES132 Applicable over recommended operating range from T Symbol Parameter Write cycle time t ...
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... See Appendix L for power up, sleep, standby, and wakeup specifications. The sleep command is described in Section 7.24. All values are preliminary and will be updated after characterization. Figure 9-1. SPI interface timing, (1) = −40° 85° +2.5V to +5. setup time at wakeup Atmel ATAES132 Preliminary Datasheet Min Typ Max Units µs 500 600 µs 1200 1500 µ ...
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... HD.STA HD.DAT +2.5V to +5.5V, CC Min Max 400 400 250 250 250 100 0 300 100 50 550 50 (1) 500 SU.DAT SU.STO BUF Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 Units MHz percent ...
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... VALID +2.5V to +5.5V, CC Min Max HI-Z Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 Units MHz percent µs µ ...
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... Temperature Sensor Characteristics Table 9-83. Temperature sensor characteristics of the Atmel ATAES132 Applicable over recommended operating range from T Symbol Parameter T Die temperature DIE T Uncalibrated temperature sensor accuracy ACCY T Calibrated temperature sensor accuracy ACCY.CAL1 t Temperature sensor read time TEMP Notes: 1. Values are based on characterization and are not tested 2 ...
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... Appendix A. Standards and Reference Documents A.1. National and International Standards The Atmel ATAES132 is designed to comply with the requirements of the AES standard. FIPS-197 Specification for the Advanced Encryption Standard (AES). 26 November 2001 Available at: http://csrc.nist.gov/groups/ST/toolkit/block_ciphers.html A.2. References SP800-38A NIST Special Publication 800-38A. Recommendation for Block Cipher Modes of Operation: Methods and Techniques ...
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... Appendix B. Memory Map B.1. The Atmel ATAES132 Memory Map Reserved memory cannot be written or read. Table B-1. The Atmel ATAES132 memory map Byte Address Description User memory 0000 -0FFF h h Reserved 1000 -EFFF h h Configuration memory – Device config F000 -F05F h h Configuration memory – CounterConfig ...
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... B.2. EEPROM Page Boundary The ATAES132 EEPROM has 32 byte physical pages. An EEPROM write can never cross the boundary between two physical pages. BlockRead and EncRead operations cannot cross the boundary between two physical pages. Table B-2 illustrates the page boundary locations for ATAES132. ...
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... User Zone 9 0900 -09FF h h User Zone A 0A00 -0AFF h h User Zone B 0B00 -0BFF h h User Zone C 0C00 -0CFF h h User Zone D 0D00 -0DFF h h User Zone E 0E00 -0EFF h h User Zone F 0F00 -0FFF h h Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 79 ...
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... See Section 6.1 for a description of the crypto command block. Write operations which begin at any other location within the buffer are invalid and will not be processed by the ATAES132. Table D-5. Command memory buffer map ...
Page 81
... ReturnCode D.3.2. Using the Response Memory Buffer After an ATAES132 command is executed, the RRDY bit of the STATUS register is set indicate that a new response is available in the response memory buffer. The host reads the response block from the buffer using one or more standard SPI ...
Page 82
... The device status register is used for handshaking between the host microcontroller and the ATAES132. The host is expected to read the STATUS register before sending a command or reading a response. See Appendix G for the definition and behavior of the STATUS register. If the ATAES132 is configured in SPI Interface mode, the STATUS register can also be read using the SPI RDSR command as described in Section K.3.6. ...
Page 83
... Appendix E. Configuration Memory Map The ATAES132 configuration memory is located from address 0xF000 to address 0xF1FF. The configuration memory can always be read using the BlockRead command (see Section 7.4). See Section E.2 for descriptions of each configuration register. A memory map showing the default register values is in Appendix O. ...
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... SmallZone is locked separately from the remainder of the configuration memory Counter 00 Counter 01 Counter 02 Counter 03 Counter 04 Counter 05 Counter 06 Counter 07 Counter 08 Counter 09 Counter 0A Counter 0B Counter 0C Counter 0D Counter 0E Counter 0F FreeSpace SmallZone Atmel ATAES132 Preliminary Datasheet / 8760A−CRYPTO−5/11 ...
Page 85
... SerialNum is an eight byte read-only register that is programmed by Atmel at the factory. The contents of this register are guaranteed to be unique on each unit over the production life of the ATAES132 product family. The contents of this register can optionally be included in the cryptographic calculations by setting mode bit described in the command definitions in Section 7 ...
Page 86
... ManufacturingID is a two byte read-only register that is programmed by Atmel at the factory. This register contains a customer spicfic value. The default ManufacturingID register contains 0x0000. This register cannot be changed by the customer. INFO DeviceNum DeviceNum register 0x0A02 0x0A 0x0A04 0x0A Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 86 ...
Page 87
... The default configuration of the PermConfig register allows the customer to control the availability of the encrypt, decrypt, and legacy commands using the ChipConfig register. However, the ChipConfig.EncDecrE bit and ChipConfig.LegacyE bit will be ignored if the ATAES132 is configured at the factory to disable external encryption (see the PermConfig Register definition in Section E.2.14). ...
Page 88
... ChipConfig.PowerUpState bits. See Appendix L for detailed information regarding the ATAES132 power management functions. The default value of the ChipConfig register is 0xC3. In this configuration, the ATAES132 goes to the active state at power up, the encrypt, decrypt and legacy commands are enabled. E.2.17. TempCal Register The TempCal register contains a value indicating the calibration procedure used to determine the TempOffset register value at the factory ...
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... KeyID of the key used to generate the Counter command input MAC for increment operations 4 to7 KeyID of the key used to generate the Counter command output MAC for counter read operations KeyConfig 0 Byte 1 Byte 2 Byte 3 Atmel ATAES132 Preliminary Datasheet CounterConfig 2 CounterConfig 3 Byte 0 Byte 1 Byte ...
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... If 1b, then this key is permitted to be the target of a KeyImport command. If 0b, then the KeyImport command is prohibited If 1b, then the KeyExport and KeyCompute commands require prior authentication using the KeyID stored in LinkPointer If 0b, then prior authentication is not required Atmel ATAES132 Preliminary Datasheet (2) 90 8760A−CRYPTO−5/11 ...
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... MAC calculation. MAC calculations will include the counter if command mode bit five is 1b even if key usage limits are disabled Reserved for future use. All bits must ZoneConfig 0 Byte 1 Byte 2 Byte 3 Atmel ATAES132 Preliminary Datasheet ZoneConfig 1 Byte 0 Byte 1 Byte 2 8760A−CRYPTO−5/ ...
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... The contents of this byte are ignored unless WriteMode contains 10b or 11b If 0x55, then the user zone is read/write If any other value, then the user zone is read-only This byte can be updated after the configuration memory is locked by using the lock command (See Section 7.19.) Atmel ATAES132 Preliminary Datasheet 92 8760A−CRYPTO−5/11 ...
Page 93
... Section E.2.11). The default value of the FreeSpace register is 0xFF in all bytes. The FreeSpace register can be programmed with any value – the contents will not change the behavior of the ATAES132. E.2.25. SmallZone Register The SmallZone register is 32 bytes of memory for storage of customer data. Optionally, the first four bytes of the SmallZone may be included in cryptographic calculations by setting mode bit described in the command definitions in Section 7 ...
Page 94
... Appendix F. Key Memory Map Table F-21. The key memory map.The ATAES132 key memory is located at address 0xF200. Address F200 -F207 h h F208 -F20F h h F210 -F217 h h F218 -F21F h h F220 -F227 h h F228 -F22F h h F230 -F237 h h F238 -F23F ...
Page 95
... STATUS register when the device address is ACKed. If the ATAES132 is in the sleep or standby power state, reading the STATUS register forces the ATAES132 to wakeup – the STATUS register is 0xFF until the wakeup process is complete. ...
Page 96
... G.1.2. WIP Status Bit [0] The WIP status bit is used to indicate the device is busy or a "Write is In Progress". If WIP = 0b, then the ATAES132 is in the active state and is waiting to receive a command. If WIP = 1b, then ATAES132 is in the active state and is performing an EEPROM write processing an ATAES132 command. ...
Page 97
... C device address operates similar to the way the WIP Status bit changes value in SPI Interface mode. G.2.1. Power Up The ATAES132 will NAK all instructions received during power up to indicate that it is not ready to accept a command from the host. When the power up process is complete (after time t ChipConfig Register bits 6 and 7 – ...
Page 98
... If the device is configured to enter the sleep state, then the ATAES132 will NAK any attempt to read the STATUS at the completion of power up as described in Section G.2.2. If the device is configured to enter the standby state, then the ATAES132 will NAK any attempt to read the STATUS at the completion of power up as described in Section G.2.3 – ChipState will remain 0xFFFF in the standby state ...
Page 99
... No ReturnCode is generated by a memory read error. G.2.6. Write User Memory The ATAES132 instructions for directly writing the user memory are identical to the standard Atmel Serial EEPROM. The host can send a write memory instruction (BWRITE, PWRITE) whenever the ATAES132 ACKs the I ...
Page 100
... ReturnCode is generated by these error conditions. The EERR Status bit buffer overrun error occurs. The EERR bit bad checksum or short count error occurs. If the Command Block contains a good checksum, then ATAES132 will process the command and load the response in the Response Memory Buffer. Upon completion of command processing the RRDY bit of the STATUS register is set shown in 0 ...
Page 101
... If the host must write the command memory buffer with more bytes than is required to send the command block due to hardware limitations, then the host should transmit 0xFF bytes after the checksum. The extra bytes will be discarded by the ATAES132 and will not result in a buffer overrun, or any other error. G.2.8. Read Response Memory Buffer ...
Page 102
... When the ATAES132 is busy or unable to respond for any reason, the WIP status bit is 1b...... G.3.1. Power Up The ATAES132 will .......... during power up to indicate that it is not ready to accept a command from the host. When the power up process is complete (after time t 6 and 7 (see Section L.2.1): the active state, the standby state, or the sleep state. ...
Page 103
... The counter registers can always be read from the configuration memory using the BlockRead command. However, the count command is the preferred method of reading the counters. When the counter is read using the count command, the ATAES132 automatically selects the appropriate counter register fields and returns them to the host in the response packet. See Section 7.5 for the counter command. ...
Page 104
... BinCount contains the BinCountB value All other values are reserved for future use Contains the Least Significant Byte of the binary counter identified in the CountFlag field Contains the Most Significant Byte of the binary counter identified in the CountFlag field Atmel ATAES132 Preliminary Datasheet 104 8760A−CRYPTO−5/11 ...
Page 105
... Appendix I. Cryptographic Computations The ATAES132 implements all its cryptographic commands using AES in CCM mode, with a 128 bit key length per NIST SP800-38C. CCM mode provides both confidentiality and integrity checking with a single key. The integrity MAC includes both the encrypted data and additional authenticate-only data bytes. The particular information authenticated with each command is described within the command descriptions in Section 7 ...
Page 106
... If 0b, the nonce value has been sent to the device by the system and may not be unique This bit is 1b for MAC values that are sent to the device as inputs This bit is 0b for MAC values output by the ATAES132 All bits must be 0b Atmel ATAES132 Preliminary Datasheet 106 8760A− ...
Page 107
... A’0 is XOR’d with the cleartext MAC and sent to the system A1 is composed of the following 128 bits: 1 byte flag, fixed value of b0000 0001 12 byte nonce, as generated by ATAES132 during nonce command 1 byte MacCount, 1 for first MAC generation 2 byte counter field – always 0x00 01 for A1 A’ ...
Page 108
... A’0 is XOR’d with the encrypted input MAC and stored in the internal SRAM as the MAC composed of the following 128 bits: 1 byte flag, fixed value of b0000 0001 12 byte nonce, as generated by ATAES132 during nonce command 1 byte MacCount, 1 for first MAC generation 2 byte counter field – always 0x00 01 for A1 A’ ...
Page 109
... If any of the optional authenticate fields are selected in the mode parameter, then a second authenticate-only block is included in the MAC calculations. 16 bytes SecondBlock field containing: 4 bytes Usage counter value, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 109 ...
Page 110
... If any of the optional authenticate fields are selected in the mode parameter, then a second authenticate-only block is included in the MAC calculations. 16 bytes SecondBlock field containing: 4 bytes Usage counter value, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 110 ...
Page 111
... If any of the optional authenticate fields are selected in the mode parameter, then a second authenticate-only block is included in the InMAC calculation. 4 bytes Usage counter value for MAC generation key, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 111 ...
Page 112
... Decrypt Command MAC In normal decryption mode, the InMAC is calculated using the following 14 bytes in the default authenticate-only block: 2 bytes ManufacturingID 1 byte Decrypt Opcode (0x07) 1 byte Mode 2 bytes Param1 2 bytes Param2 1 byte MacFlag 5 bytes 0x00 Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 112 ...
Page 113
... If any of the optional authenticate fields are selected in the mode parameter, then a second authenticate-only block is included in the MAC calculation. 4 bytes Usage counter value, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 113 ...
Page 114
... MacCount, 1 for first MAC generation 2 byte counter field – always 0x00 00 A’0 is XOR’d with the clear text MAC and sent to the system Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 114 ...
Page 115
... MacCount, 1 for first MAC generation 2 byte counter field – always 0x00 00 A’0 is XOR’d with the clear text MAC and sent to the system Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 115 ...
Page 116
... Usage counter value, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected I.21. Info Command The Info command does not perform a cryptographic operation and does not use or generate a MAC. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 116 ...
Page 117
... KeyExport Command – KeyLoad MAC The MAC is calculated using the following 14 bytes in the default authenticate-only block: 2 bytes ManufacturingID 1 byte KeyLoad Opcode (0x09) 6 bytes FirstBlock field containing: 1 byte Mode 2 bytes Param1 2 bytes Param2 1 byte MacFlag 5 bytes 0x00 Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 117 ...
Page 118
... If any of the optional authenticate fields are selected in the mode parameter, then a second authenticate-only block is included in the MAC calculation. 16 bytes SecondBlock field containing: 4 bytes Usage counter value, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 118 ...
Page 119
... If any of the optional authenticate fields are selected in the mode parameter, then a second authenticate-only block is included in the MAC calculation. 4 bytes Usage counter value, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected The AES key used for the MAC calculation is that specified in ZoneConfig[Zone].WriteID Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 119 ...
Page 120
... The reset command does not perform a cryptographic operation and does not use or generate a MAC. I.35. Sleep Command The sleep command does not perform a cryptographic operation and does not use or generate a MAC. I.36. TempSense Command The TempSense command does not perform a cryptographic operation and does not use or generate a MAC. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 120 ...
Page 121
... If any of the optional authenticate fields are selected in the mode parameter, then a second authenticate-only block is included in the MAC calculation. 16 bytes SecondBlock field containing: 4 bytes Usage counter value, or 0x00 if not selected 8 bytes SerialNum[0:7], or 0x00 if not selected 4 bytes SmallZone[0:3], or 0x00 if not selected Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 121 ...
Page 122
... Atmel I The host sends ATAES132 extended commands to the device by writing the command packet to the command memory buffer at address 0xFE00. The ATAES132 processes the command packet and places the response in the response memory buffer. ...
Page 123
... J.1. ACK All addresses and data words are serially transmitted to and from the ATAES132 in 8-bit words. The receiving I sends a zero (ACK) during the ninth clock cycle to acknowledge receipt of each byte Host can use acknowledge polling to monitor the progress of an EEPROM write and to determine if the slave is ready to accept a new instruction ...
Page 124
... Serial Clock input pin. In the I C communication mode, this pin is used as the serial interface clock (SCK). The SCK input is used to transfer data in to the ATAES132 on the rising edge of clock and to transfer data out on the falling edge of clock. The ATAES132 never drives SCK because standard-mode I The SCK line is high when the bus is idle ...
Page 125
... STOP condition after the first data byte is clocked in. Instead, after the device ACKs receipt of the first data byte, the host microcontroller can transmit more data bytes (each byte will be ACKed by the ATAES132). The EEPROM will respond with an I sequence with a STOP condition ...
Page 126
... A random read requires a “dummy” byte write sequence to load in the data byte address. Once the device address and data byte address are clocked in and acknowledged by the ATAES132, the host microcontroller must generate another start condition. The microcontroller then initiates a current address read by sending the device address with the read/write select bit 2 high (READ) ...
Page 127
... A DATA J.3.7. Software Reset (SRESET) After an interruption in protocol, power loss or system reset, the ATAES132 in I following these steps: • Send a START condition • Clock 9 cycles • Send another START condition followed by STOP condition as shown below The device is ready for next communication after these steps have been completed. The internal data address is also reset to 0000h by this procedure ...
Page 128
... Start bit SCL 1 SDA The ATAES132 requires that the clock be pulled low between the START condition and the STOP condition at the end of the sequence as illustrated in Figure J-7, it will not reset if this clock transition is omitted. See Section J.4 for detailed I resynchronization instructions. J.3.8. Acknowledge Polling The host can initiate an acknowledge (ACK) polling immediately after a write command or the ATAES132 extended Crypto command is transmitted ...
Page 129
... The ATAES132 will not respond • The ATAES132 may be damaged if the clock or data signal levels are above V ATAES132 cannot be switched off while the bus is active. All of the voltage limits in Section 9.1 must be respected. Operation First successful Auth command forces AuthO high. Additional Auth commands do not change AuthO, AuthO output remains latched high ...
Page 130
... The ATAES132 inputs include Schmitt triggers and spike suppression, however, the outputs do not include falling edge slope control. • devices a START condition followed immediately by a STOP condition is never permitted. On ATAES132 this sequence is permitted only as part of the SRESET command sequence (see Section J.3.7). ...
Page 131
... SPI instruction code is complete, then the interface invalid instruction code is received, then the ATAES132 will ignore any data received on the data input pin (SI), and the data output pin (SO) will remain in a high impedance state. K.1.5. Data Format All instructions and data on the SPI bus must be formatted as eight bit bytes ...
Page 132
... K.2.1. [Pin 1] SPI chip select bar input pin. In SPI communication mode, this pin functions as the slave select input. ATAES132 is selected when the pin is low, allowing instructions and data to be accepted on the serial data input pin (SI), and allowing data to be transmitted on the serial data output pin (SO). When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state ...
Page 133
... WREN 0000 0110 b If the ATAES132 receives an invalid instruction code or an invalid memory address, then no response will be sent – the SO output will remain in the high impedance state. When any error occurs, the EERR bit of the STATUS register is set indicate an error. The host can read the error code from the response memory buffer at address 0xFE00 using the READ command ...
Page 134
... SO K.3.4. Read Memory Command (READ): Reading data from the ATAES132 requires the following sequence. The host drives the transmits the read instruction code on the SI line followed by the address of the byte to be read. The client ignores any data on the SI line which follows a read memory instruction. ...
Page 135
... The ready/busy status of the device can be determined by initiating a read status register (RDSR) instruction. If the WIP status bit is 1b, the write cycle is still in progress. If the WIP status bit is 0b, the write cycle has ended and the ATAES132 is ready to accept a new command. Only the read status register (RDSR) instruction is enabled during the EEPROM write cycle. ...
Page 136
... The device status register can always be read, even if the the ATAES132 is processing a command or writing the EEPROM. The SPI RDSR command is the preferred method for reading the STATUS in SPI interface mode. If the ATAES132 is in the sleep or standby power state, reading the STATUS register forces the ATAES132 to wakeup – the STATUS register is 0xFF until the wakeup process is complete. ...
Page 137
... SCK HI DATA OUT MSB VALID Atmel ATAES132 Preliminary Datasheet HI-Z 8760A−CRYPTO−5/11 137 ...
Page 138
... The ATAES132 is in the active state after it has completed the power up process and is fully powered. The WIP status bit is 0b when the ATAES132 is in the active state and waiting for a command. The WIP status bit is 1b when the ATAES132 is in the active state and processing a command or performing an EEPROM write ...
Page 139
... Entering the Standby State If the ATAES132 is in the active state, the host can send a sleep command to place the ATAES132 in the standby state. (See Section 7.24 not possible to transition the device directly from the sleep state to the standby state. The host must wakeup the device and then must send a sleep command to place the device in standby ...
Page 140
... Entering the Sleep State If the ATAES132 is in the active state, the host can send a sleep command to place the ATAES132 in the sleep state. (See Section 7.24 not possible to transition the device directly from the standby state to the sleep state. The host must wakeup the device and then must send a sleep command to place the device in sleep ...
Page 141
... C device address. The ATAES132 will answer the ACK poll with an I The ACK poll reply will change to ACK when the device is in the active state. The ATAES132 will not accept any commands while it is "busy". The ATAES132 will NAK the I 2 not match the internal I ...
Page 142
... L.3.4. Events that Do Not Change ChipState The following events cause NO CHANGE in the ChipState register value. These events do not modify the security state of the ATAES132 and therefore do not cause the ChipState to change. Table L-44. Description of events causing NO CHANGE in the ChipState register Event Event description WakeUp from Standby WakeUp from the Standby Power State (Section L ...
Page 143
... SPI Write SPI standard write beginning at any user zone address, any configuration memory address, or any key memory address [WREN, WRITE, WRDI instructions] (Section K.3) C standard write beginning at any user zone address, any configuration memory address, or Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 143 ...
Page 144
... An Atmel CRC-16 checksum is used to verify the integrity of blocks communicated to and from the ATAES132. The host sends ATAES132 extended commands to the device in a block of at least four bytes. The ATAES132 responses are returned to the host in a block of at least four bytes. The command and response blocks are constructed in the following ...
Page 145
... M.2. Checksum Examples DATA = CRC = 0xF960 Atmel ATAES132 Preliminary Datasheet 145 8760A−CRYPTO−5/11 ...
Page 146
... Appendix N. Atmel ATAES132 Command Response Time The typical and maximum time required for the ATAES132 to process an extended command is shown in Table N-1. The response time is the time from sending the last bit of the last byte of the command block to the command memory buffer until ...
Page 147
... KeyExport, with RNG Seed Update. (Mode [5:7] not 000b), with Key Usage KeyImport (Mode [5:7] = 000b) KeyImport (Mode [5:7] not 000b) KeyImport (Mode [5:7] not 000b), with Key Usage Typical time 2.9 milliseconds (5) 2.3 milliseconds (5) (5) 2.3 milliseconds (5) 2.8 milliseconds (5) 4.1 milliseconds (5) (5) (5) (5) Atmel ATAES132 Preliminary Datasheet (2) (3) Maximum time 14.2 milliseconds 14.4 milliseconds 26 milliseconds 147 8760A−CRYPTO−5/11 ...
Page 148
... These times are with the key usage limits enabled in the KeyConfig register. All other times are with the key usage limits disabled in the KeyConfig register. All values are preliminary and will be updated after characterization. Typical time (5) (5) (5) 0.5 milliseconds 7.5 milliseconds 0.5 milliseconds 7.0 milliseconds 80 milliseconds (5) (5) Atmel ATAES132 Preliminary Datasheet (2) (3) Maximum time 11 milliseconds 11 milliseconds 145 milliseconds 148 8760A−CRYPTO−5/11 ...
Page 149
... Appendix O. Default Configuration The ATAES132 memory map is shown in Table O-1 with the default memory values. Reserved memory cannot be written or read. Table O-47. The Atmel ATAES132 memory map showing the default memory contents Byte Address Description 0000 -0FFF User memory [Default = All Bytes ...
Page 150
... Atmel ATAES132 Preliminary Datasheet Atmel proprietary data Atmel proprietary data 00 03 Atmel data TempOffset value ...
Page 151
... Interface mode. The default value of I Atmel ATAES132 Preliminary Datasheet ...
Page 152
... The key memory contains pseudorandom values after completion of production test, except for key 00 which contains the transport key. Device personalization can be performed without knowledge of the Transport Key, however, secure personalization can only be performed if the transport key value has been obtained from Atmel. Atmel ATAES132 Preliminary Datasheet 8760A−CRYPTO−5/11 152 ...
Page 153
... EEPROM write after receiving a STOP condition. Partial page writes are supported by the AT24C32C. The ATAES132 does not allow write operations to cross physical (32 byte) EEPROM page boundaries (see Section B.2), and does not allow a write operation if more than 32 data bytes are received from the host. In both cases the EEPROM contents remain unchanged, the data is discarded, and an error bit is set in the STATUS register (see Section J ...
Page 154
... The read operation continues from address zero ATAES132 read operation begins at a valid user memory address but continues past the end of user memory, the read operation will not wrap to the beginning of user memory. Reading beyond the end of user memory causes 0xFF to be returned to the host in reply to the read, the internal data address register stops incrementing, and an error bit is set in the STATUS register (see Section G ...
Page 155
... The read operation continues from address zero ATAES132 read operation begins at a valid user memory address but continues past the end of user memory, the read operation will not wrap to the beginning of user memory. Reading beyond the end of user memory causes 0xFF to be returned to the host in reply to the read, the internal data address register stops incrementing, and an error bit is set in the STATUS register ...
Page 156
... The ATAES132 will remain in the active state between operations unless the host sends a sleep command to activate the standby state or the sleep state. The ATAES132 can also be configured to automatically enter a low power state at power up. See Appendix L for details on the power management features. ...
Page 157
... ATAES132 standard packages are marked with a trace code which is unique for each manufacturing lot. Contact Atmel for additional information. Atmel Ordering Codes Atmel ordering code ATAES132-SH-EQ ATAES132-SH-ER ATAES132-SH-FB ATAES132-SH-EQ-T ATAES132-SH-ER-T ATAES132-SH-FB-T ATAES132-TH-EQ ATAES132-TH-ER ATAES132-TH-FB ATAES132-TH-EQ-T ATAES132-TH-ER-T ATAES132-TH-FB-T ...
Page 158
... Package Drawing Contact: packagedrawings@atmel.com END VIEW SYMBOL TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) Atmel ATAES132 Preliminary Datasheet COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOM NOTE 1.35 – 1.75 0.10 – 0.25 0.31 – 0.51 0.17 – ...
Page 159
... Package Drawing Contact: packagedrawings@atmel.com E End View MIN SYMBOL D 2.90 E 6.40 BSC E1 4. 0. 0.45 L1 TITLE 8A2, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Atmel ATAES132 Preliminary Datasheet L1 L COMMON DIMENSIONS (Unit of Measure = mm) MAX NOM NOTE 3.00 3. 4.40 4. – – 1.20 1.00 1.05 – 0.30 4 0.65 BSC 0.60 ...
Page 160
... ccc eee TITLE 8MA3, 8-pad 0.6 mm Body, 0.5 mm Pitch, 1.6 x 0.2 mm Exposed Pad, Saw Singulated Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN/USON) Atmel ATAES132 Preliminary Datasheet 1.50 Ref R0. 0.10mm COMMON DIMENSIONS (Unit of Measure = mm) ...
Page 161
... PermConfig register is at address 0xF02D, and the ManufacturingID register is at address 0xF02B to 0xF02C. The TempCal register did not exist in first silicon. The TempOffset register was two bytes in first silicon, but was expanded to accommodate improved temperature sensor calibration procedures. Table R-51. Partial configuration memory map for the Atmel ATAES132 first silicon Address 0 ...
Page 162
... R.1. Data In Hold Time 2 The minimum I C data in Hold time specification is 0ns. This revision of the ATAES132 requires 10ns minimum I Hold time. This problem will be fixed in future revisions of ATAES132. R.1.9. EncWrite to Key Memory The EncWrite command should permit key memory to be written using encrypted data as described in Section 7.11. Actual behavior is that the EncWrite command appears to function correctly when writing to key memory, however, the new contents of the key register will be incorrect ...
Page 163
... I CAddr register correctly resulting in selection of the wrong interface mode or loading a random I device address result it may be impossible for the host microcontroller to communicate with the ATAES132. Selection of the wrong interface mode at power up could result in permanent damage to the ATAES132. ...
Page 164
... Actual behavior in the I C interface mode is that the RRDY bit is not reset when an invalid address read is attempted – if the RRDY bit is 1b before the read, then it remains 1b. ATAES132 operates correctly in SPI Interface mode. This problem will be fixed in future revisions of ATAES132 R.2.5. EERR and RRDY Status bits Reset by not polling during command execution ...
Page 165
... Appendix S. Revision History Doc. Rev. Date 8760A 05/2011 Comments Initial document release Atmel ATAES132 Preliminary Datasheet 165 8760A−CRYPTO−5/11 ...
Page 166
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...