ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 131

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

Appendix K. SPI Interface
K.1.
K.1.1. SPI Master
K.1.2. SPI Slave
K.1.3. Relationship of Clock to Data
K.1.4. SPI Instruction Code
K.1.5. Data Format
The ATAES132 serial peripheral interface (SPI) is designed to interface directly to the microcontrollers using SPI Mode 0 or
Mode 3. IO and clear-text read/write operations operate similar to the Atmel SPI serial EEPROM.
The host sends ATAES132 commands to the device by writing the command packet to the command memory buffer at
address 0xFE00. The ATAES132 processes the command packet and places the response in the response memory buffer.
The host retrieves the response by reading the response packet from address 0xFE00.
See Section G.3 for additional information on the ATAES132 behavior in SPI interface mode.
SPI Serial Interface Description
When the ATAES132 is configured in the SPI communication mode, the serial interface operates as a Mode 0 and Mode 3
slave device as described in this appendix. Serial peripheral interface (SPI) is a synchronous serial interface protocol that is a
defacto industry standard which is not formally documented or controlled. Multiple SPI devices can share the data bus,
however, each SPI slave must have a separate
The serial interface communication mode is selected by programming the I
described in Section E.2.15.
The SPI bus master device generates the serial clock and sends instructions to the SPI slave devices. In this specification, the
bus master is usually referred to as the host or the host microcontroller.
SPI slave devices receive the serial clock as an input and receive instructions from the bus master. SPI slaves can never
generate traffic on the SPI bus, slaves can only respond to instructions provided by the bus master. The ATAES132 always
operates as a slave. In this specification the slave is usually referred to as the client.
The ATAES132 supports two of the four standard SPI interface modes, Mode 0 and Mode 3.
In Mode 0, the default state of SCK is low, and the data is clocked in (SI) on the rising edge of the clock. Data out (SO)
changes on the falling edge of the clock.
In Mode 3, the default state of SCK is high, and data is clocked in (SI) on the rising edge of the clock. Data out (SO) changes
on the falling edge of the clock.
Each SPI command begins with the SPI master bring the
eight bit SPI instruction code to the SI input of the SPI slave. Following the instruction code, additional bytes may be clocked
into SI or out of SO as required by the SPI command (see Section K.3 for SPI command definitions). When the exchange of
data bytes related to the SPI instruction code is complete, then the
interface.
If an invalid instruction code is received, then the ATAES132 will ignore any data received on the data input pin (SI), and the
data output pin (SO) will remain in a high impedance state.
All instructions and data on the SPI bus must be formatted as eight bit bytes. The MSB is the first bit of each byte transmitted
and received.
control line to prevent bus contention.
input low to select the device, followed by transmission of an
input is brought high to deactivate the SPI slave
Atmel ATAES132 Preliminary Datasheet
2
CAddr register in the configuration memory as
8760A−CRYPTO−5/11
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