ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 97

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

G.1.8. Reserved Status Bits [3, 5]
G.2.
G.2.1. Power Up
The EERR status bit will be set to 1b if an SPI or I
protected portion of the memory. EERR will also be set to 1b if an SPI or I
continues into protected memory. In both of these cases, the RRDY status bit is 0b and the response memory buffer will
remain empty because these errors do not generate a ReturnCode. Reading beyond the end of user zone F will not cause the
EERR bit to be set to 1b.
Note:
The reserved status bits are always 0b when the ATAES132 is capable of accepting a command. The reserved status bits are
1b during power up and during wakeup from the sleep state or the standby state.
STATUS Register Behavior in the I
The following sections describe the device behavior and expected STATUS register values during commonly performed
operations. In the I
address. The ATAES132 will ACK instructions with a matching I
instruction. See Appendix J for the I
When the ATAES132 is busy or unable to respond for any reason, it will NAK a matching I
response to the I
The ATAES132 will NAK all instructions received during power up to indicate that it is not ready to accept a command from the
host. When the power up process is complete (after time t
ChipConfig Register bits 6 and 7 – the active state, the standby state, or the sleep state (see Section L.2.1). In I
mode, it is impossible to read the STATUS register until the completion of power up.
Upon completion of power up, the command memory buffer is empty, the response memory buffer are all 0xFF's, and the
ChipState = 0xFFFF. The default EEPROM address is set to 0x0000, and the command and response memory buffer
pointers are set to the base address of the buffers. If the device is configured to enter the active state at power up, then the
STATUS will be 0x00 as shown in Table G-3.
Table G-24. After power up to the active state, the STATUS register contains:
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
If an SPI or I
set to 1b.
2
C device address operates similar to the way the WIP Status bit changes value in SPI Interface mode.
2
C Interface mode, the ATAES132 will always NAK instructions containing a non-matching I
Definition
“0b” indicates the device is ready, waiting for a command
"0b" indicates the device is in I
"0b" indicates the device is not in the sleep or standby power state
Always "0b"
"0b" indicates no checksum error
Always "0b"
"0b" indicates the response memory buffer is empty
"0b" indicates no errors during execution
2
C read begins at an authorized address and continues into protected memory, the EERR bit will be
2
C interface specifications.
2
C Interface Mode
2
C read is attempted using an invalid address, or an address pointing to a
2
C interface mode
PU.RDY
2
), then the ATAES132 will enter the state specified by
C device address if the device is capable of accepting an
Atmel ATAES132 Preliminary Datasheet
2
C read begins at an authorized address, but
2
C device address. The ACK/NAK
8760A−CRYPTO−5/11
2
C device
2
C Interface
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