ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 82

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

D.4.
D.5.
IO Address Reset Register
Writing the IO address reset register (address 0xFFE0) with any value causes the address pointers in the command memory
buffer and the response memory buffer to be reset to the base address of the buffer. The IO address reset register can be
written with 1 to 32 bytes of data without generating an error; the data bytes will be ignored.
Writing the IO address reset register does not alter the contents of the response memory buffer, or the value of the STATUS
register. Writing the IO address reset register clears the command memory buffer (See Appendix G for examples).
Device Status Register (STATUS)
The device status register is used for handshaking between the host microcontroller and the ATAES132. The host is expected
to read the STATUS register before sending a command or reading a response. See Appendix G for the definition and
behavior of the STATUS register. If the ATAES132 is configured in SPI Interface mode, the STATUS register can also be read
using the SPI RDSR command as described in Section K.3.6.
Reading the STATUS register does not alter the contents of the command memory buffer, the response memory buffer, or the
value of the STATUS register.
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
82