ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 142

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

L.3.3.
L.3.4.
ChipState = "WakeUp from Sleep"
The following events cause the ChipState register to be set to the "WakeUp from Sleep" state (0x5555). The events in this
table cause the security registers to be cleared, the logic reinitialized, and the device returned to the active power state (ready
to receive a command).
Table L-43. Description of events causing the ChipState register to be set to 0x5555
Events that Do Not Change ChipState
The following events cause NO CHANGE in the ChipState register value. These events do not modify the security state of the
ATAES132 and therefore do not cause the ChipState to change.
Table L-44. Description of events causing NO CHANGE in the ChipState register
Notes:
Event
WakeUp from Sleep
Reset Command
Tamper
Event
WakeUp from Standby
Reading STATUS
Writing IO Address
Reset
Reading a Response
Command CRC Error
Command Invalid
ACK Polling
I
Invalid I
I
SPI Read
Invalid SPI Write
Info Command
2
2
C Read
C SRESET
2
1.
C Write
2. Writing the command memory buffer (address 0xFE00) may or may not change the ChipState, depending on
A CRCE error results from a command block with a short count, bad checksum, or a buffer overrun
which command is written to the buffer
Event description
WakeUp from the Sleep Power State (Section L.1.3)
Device receives a valid Reset command block. (Section 7.23)
Device reset initiated by the tamper sensors. (Section 3.1.2)
Event description
WakeUp from the Standby Power State (Section L.1.2)
Reading the STATUS register with SPI RDSR or standard read commands (Appendix G)
Writing the IO address reset register (Section D.4)
Reading the response memory buffer (Section D.3)
Device receives ANY command block which results in a CRCE Error
Device receives a command block containing an undefined/invalid Opcode (Section 6.2)
I
I
I
address 0xFE00 [BWRITE, PWRITE instructions]
I
SPI standard read [READ instruction] (Section K.3.4)
SPI standard write beginning at any address from 0x1000 to 0xEFFF or above 0xF300, except
address 0xFE00 [WREN, WRITE, WRDI instructions]
Device receives a valid info command block (Section 7.12)
2
2
2
2
C acknowledge polling (Section J.3.8)
C standard read [READ, RREAD, SREAD instructions] (Section J.3)
C standard write beginning at any address from 0x1000 to 0xEFFF or above 0xF300, except
C SRESET instruction (Section J.3.7)
Atmel ATAES132 Preliminary Datasheet
(2)
(Section J.3)
(2)
(Section K.3)
(1)
(Section G.1.5)
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