ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 135

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

K.3.5. Write Memory Command (WRITE):
K.3.6. Read Status Register Command (RDSR):
In order to write to the ATAES132, two separate instructions must be executed. First, the device must be write enabled via the
write enable (WREN) instruction. Then a write memory instruction may be executed. All commands received while a write
cycle is in progress will be ignored except the read status register (RDSR) instruction.
A write memory command requires the following sequence. The host drives the
transmits the write instruction code on the SI line followed by the address of the byte to write and the 1 to 32 data bytes to be
written. The byte address is automatically incremented as each byte is clocked in. The
during the SCK low time immediately after clocking in the last data bit. The low-to-high transition of the
EEPROM write process. The SO pin remains in the high impedance state during the entire write sequence.
The ready/busy status of the device can be determined by initiating a read status register (RDSR) instruction. If the WIP status
bit is 1b, the write cycle is still in progress. If the WIP status bit is 0b, the write cycle has ended and the ATAES132 is ready to
accept a new command. Only the read status register (RDSR) instruction is enabled during the EEPROM write cycle.
The ATAES132 is capable of a 32-byte page write operation. After each byte of data is received, the data address is internally
incremented by one. If more than 32 bytes of data are transmitted or if the page boundary is crossed, then no data will be
written. The ATAES132 is automatically returned to the write disable state at the completion of a write cycle.
Figure K-14. SPI WRITE memory timing
When any error occurs, the RRDY and EERR bits of the STATUS register are set to 1b to indicate an error. The host can read
the error code from the response memory buffer (address 0xFE00) using the READ command. If the command is processed
without error, the EERR bit is set to 0b. Reading the response memory buffer does not reset the error code or the STATUS
register .
If the device is not write enabled (WREN), the device will ignore the write instruction and will return to the waiting for a
command. A new
The read status register instruction provides access to the STATUS register. The ready/busy status of the device can be
determined using the RDSR instruction. Alternately, the STATUS register can be read directly from memory as described in
Section G.2.4.
If the ATAES132 is performing an EEPROM memory write or is processing a command when the STATUS read is performed,
then all eight bits are ones if the RDSR command is used to read the STATUS register, emulating the behavior of Atmel Serial
EEPROM. See Appendix G for a detailed description of the STATUS register bits and status bit behavior.
SCK
SO
CS
SI
HIGH IMPEDANCE
0
INSTRUCTION
falling edge is required prior to the new instruction code.
1
2
3
4
5
6
7
8
BYTE ADDRESS
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
Atmel ATAES132 Preliminary Datasheet
line low to select a device and then
DATA IN
line must be driven high by the host
8760A−CRYPTO−5/11
pin initiated the
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