ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 128

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

J.3.8.
J.4.
J.5.
Figure J-7.
The ATAES132 requires that the clock be pulled low between the START condition and the STOP condition at the end of the
sequence as illustrated in Figure J-7, it will not reset if this clock transition is omitted. See Section J.4 for detailed I
resynchronization instructions.
Acknowledge Polling
The host can initiate an acknowledge (ACK) polling immediately after a write command or the ATAES132 extended Crypto
command is transmitted. Acknowledge polling involves sending a START condition followed by the I
read/write bit of the I
During an EEPROM write operation, the ATAES132 will NAK the I
internal write cycle has completed, then the ATAES132 will ACK the I
to continue. The ATAES132 also NAKs during the processing of Crypto commands, so Acknowledge polling can also be used
to determine when processing of the ATAES132 extended commands is complete.
Figure J-8.
DATA OUT
I
If the host and client I
followed by the SRESET command to reset the ATAES132 interface. See Section J.3.7 for a description of the SRESET
command.
I
The Auth signaling option allows an authentication signal (AuthO) to be output by the ATAES132. Auth signaling is available
only in the I
SDA
SCL
2
2
C Interface Synchronization Procedure
C Auth Signaling
DATA IN
SCL
2
C Interface mode in standard plastic packages.
Start bit
Software reset
Output acknowledge (I
S
T
A
R
2
C device address is representative of the operation desired by the host.
T
2
C interfaces lose synchronization for any reason, the host should send clocks until SDA goes high,
1
1
2
C ACK)
2
Dummy Clock Cycles
3
8
A
C
K
N
O
2
C device address, indicating the device is "busy". When the
W
9
8
L
2
C device address, allowing the read or write sequence
E
D
Atmel ATAES132 Preliminary Datasheet
G
E
9
Start bit
2
C device address. The
8760A−CRYPTO−5/11
Stop bit
2
C interface
128