ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 80

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

Appendix D. Command Memory Map
D.2.
The ATAES132 commands are executed by writing the command packet to the virtual memory using the standard SPI or I
write commands. The response packet is retrieved by reading it from the virtual memory using the standard SPI or I
commands. The command/response memory buffer is 64 bytes.
The ATAES132 commands are executed by writing the command packet to virtual memory at starting address 0xFE00 using
the standard write commands (see Appendix J and Appendix K). The response packet is retrieved by reading from the virtual
memory at starting address 0xFE00 using the standard read commands. The device status register (STATUS) is located at
0xFFF0 (see Appendix G).
To reset the address pointer in the command/response memory buffer to the base address of the buffer, the host writes one or
more bytes to the IO address reset register at address 0xFFE0 using the standard write command. Any value can be written
to the IO address reset register to reset the buffer address pointer.
Table D-4.
Command Memory Buffer
The command memory buffer is a write-only buffer memory that is used by writing a command block to the buffer at the base
address of 0xFE00. After the host completes its write operation to the buffer, the ATAES132 verifies the integrity of the block
by checking the 16-bit checksum, and then executes the requested operation. See Section 6.1 for a description of the crypto
command block.
Write operations which begin at any other location within the buffer are invalid and will not be processed by the ATAES132.
Table D-5.
Byte address
FE00
FE01
FFE0
FFE1
FFF0
FFF1
address
Count
Base
h
h
h
h
h
h
-FFDF
-FFFF
-FFEF
Command/response virtual memory map
h
Command memory buffer map
h
h
Opcode
Base
+ 1
Description
Command/response memory buffer
Reserved
IO address reset
Reserved
STATUS register
Reserved
Mode
Base
+ 2
Param1
Base
+ 3
Param1
......
Param2
......
Atmel ATAES132 Preliminary Datasheet
.......
......
DataX
......
8760A−CRYPTO−5/11
CRC1
+ N-2
Base
2
CRC2
C read
+ N-1
Base
2
C
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