ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 134

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

K.3.3. Write Disable Command (WRDI):
K.3.4. Read Memory Command (READ):
The write enable flag can be disabled by sending the write disable instruction.
Figure K-12. SPI write disable (WRDI) timing
SCK
Reading data from the ATAES132 requires the following sequence. The host drives the
transmits the read instruction code on the SI line followed by the address of the byte to be read. The client ignores any data on
the SI line which follows a read memory instruction.
The client shifts out the data at the specified address on the SO line. If only one byte is to be read, the
high after the data byte comes out. If multiple bytes are to be read, the host can sequentially clock the data out of the
ATAES132 since the byte address is automatically incremented. The
byte is read. If the highest address is reached, the address counter will not roll over.
Figure K-13. SPI READ memory timing
When any error occurs, the EERR bit of the STATUS register is set to 1b to indicate an error. If the command is processed
without error the EERR bit is set to 0b.
Note:
SCK
CS
SO
SO
CS
SI
SI
HIGH IMPEDANCE
If an SPI read begins at an authorized address, but continues into protected memory the EERR bit will be set to
1b
0
INSTRUCTION
1
2
3
4
5
6
7
15 14 13 ... 3
8
9
WRDI OP-CODE
BYTE ADDRESS
10 11 20 21 22 23 24 25 26 27 28 29 30 31
HI-Z
2
1
0
MSB
Atmel ATAES132 Preliminary Datasheet
line must be driven high by the host after the last data
7
6
5
DATA OUT
4
3
line low to select a device and then
2
1
0
8760A−CRYPTO−5/11
line must be driven
134