5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet
5SGXEA4H2F35I3LN
Specifications of 5SGXEA4H2F35I3LN
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5SGXEA4H2F35I3LN Summary of contents
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www ...
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... Also common to Stratix V devices is the new Embedded HardCopy Block, which is a customizable hard IP block that leverages Altera’s unique HardCopy ASIC capabilities. The Embedded HardCopy Block in Stratix V FPGAs is used to harden IP instantiation of PCIe Gen3, Gen2, and Gen1. Stratix V Device Overview Stratix V Family Variants December 2012 Altera Corporation ...
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... High-performance core fabric ■ Enhanced ALM with four registers ■ Improved routing architecture reduces congestion and ■ improves compile times December 2012 Altera Corporation Embedded memory blocks ■ M20K: 20-Kbit with hard error correction code (ECC) ■ MLAB: 640-bit ■ Variable precision DSP blocks ■ ...
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... Package information datasheet for Altera and to AN 644: Migration Between Stratix V GX and Stratix V GT Stratix V Family Plan 5SGTC7 425 622 642 939 4/32 4/ 2,560 45 50 512 512 256 256 4 4 5SGTC7 600, 150, 36 devices. Devices. December 2012 Altera Corporation ...
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Table 2 lists the Stratix V GX device features. Table 2. Stratix V GX Device Features (Part Features 5SGXA3 5SGXA4 Logic Elements (K) 340 420 Registers (K) 513 634 14.1-Gbps Transceivers 12, 24 ...
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Table 2. Stratix V GX Device Features (Part Features 5SGXA3 5SGXA4 Notes to Table 2: (1) The F1517 package contains 24 PLLs. The other packages with this device contain 20 PLLs. (2) Packages are flipchip ball grid ...
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... Hybrid packages are slightly larger than conventional FBGAs. Refer to Altera’s packaging documentation for more information. (6) Migration between select Stratix V GS devices and Stratix V GX devices is available. For more information, refer to December 2012 Altera Corporation 5SGSD3 5SGSD4 ...
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... Hybrid packages Stratix V Family Plan 5SEE9 5SEEB 840 952 1,268 1,437 28 28 2,640 2,640 52 52 704 704 352 352 6 6 5SEE9 5SEEB H H 696, 174 696, 174 840, 210 840, 210 December 2012 Altera Corporation ...
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Each row in Table 5 lists which devices allow migration. Table 5. Device Migration List Across All Stratix V Device Variants Package EH29-H780 Yes (2) HF35-F1152 Yes Yes Yes KF35-F1152 Yes Yes Yes KF40-F1517 / Yes Yes ...
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... You can use the unused transceiver channels as additional transceiver transmitter PLLs. Stratix V Device Overview Table 6 lists the transceiver PMA features. (1) Core Logic Fabric Low-Power Serial Transceivers PCS PMA PCS PMA PCS PMA PCS PMA PCS PMA (2) December 2012 Altera Corporation ...
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... Custom 10G PHY 9.98 to 14.1 x1, x4, x8 PCIe 2.5 and 5.0 Gen1 and Gen2 December 2012 Altera Corporation Capability 14.1 Gbps (Stratix V GX and GS devices), 12.5 Gbps (Stratix V GT devices) PCIe cable and eSATA applications 10G Form-factor Pluggable (XFP), Small Form-factor Pluggable (SFP+), Quad Small Form-factor Pluggable (QSFP), CXP, 100G Pluggable (CFP), 100G Form- factor Pluggable 28 ...
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... Same as custom PHY plus GbE state machine Same as custom PHY plus XAUI state machine for re-aligning four channels Same as custom PHY plus SRIO V2.1-compliant x2 and x4 deskew state machine Same as custom PHY plus RX deterministic latency Same as custom PHY December 2012 Altera Corporation ...
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... The Quartus II software leverages the Stratix V ALM logic structure to deliver the highest performance, optimal logic usage, and lowest compile times. The Quartus II software simplifies design re-use because it automatically maps legacy Stratix designs into the new Stratix V ALM architecture. December 2012 Altera Corporation ® IP that simplifies a design for today’s advanced Table 8 lists external memory interface block performance ...
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... The Quartus II software simplifies design re-use by automatically mapping memory blocks from legacy Stratix devices into the Stratix V memory architecture. Stratix V Device Overview Table 9. MLAB (640 Bits) 32x20 64x10 Clocking M20K (20,480 Bits) 512x40 1Kx20 2Kx10 4Kx5 8Kx2 16Kx1 December 2012 Altera Corporation ...
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... Efficient support for single- and double-precision floating point arithmetic ■ Ability to infer all the DSP block modes through HDL code using the Altera Complete Design Suite December 2012 Altera Corporation Table 10 describes how Expected Usage Low precision fixed point Medium precision fixed point ...
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... Different designers or IP providers can develop and optimize different blocks of the design independently, which you can then import into the top-level project. Stratix V Device Overview Power Management December 2012 Altera Corporation ...
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... FPGA functions that do not operate simultaneously. Instead, you can store these functions in external memory and load them as required. This capability reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power. December 2012 Altera Corporation Remote Encryption Update ...
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... FPGA-based systems, Altera provides the optimal solution for power, performance, and device bandwidth. Stratix V Device Overview Automatic Single Event Upset Error Detection and Correction ® II processor. December 2012 Altera Corporation ...
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... Note to Figure 2: (1) You can select one or both of these options, or you can ignore these options. December 2012 Altera Corporation Package Type Transceiver Count F : FineLine BGA Hybrid FineLine BGA Operating Temperature Commercial ( ° ...
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... Updated tables listing device features. ■ Added device migration information. ■ Updated 12.5-Gbps transceivers to 14.1-Gbps transceivers ■ Updated Table 1-1. Updated Table 1-1. ■ Updated Figure 1-2. ■ Converted to the new template. ■ Minor text edits. ■ Updated Table 1–5 Revision History December 2012 Altera Corporation ...
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... Date Version July 2010 1.2 May 2010 1.1 April 2010 1.0 December 2012 Altera Corporation Changes Made Updated “Features Summary” on page 1–2 ■ Updated resource counts in Table 1–1 and Table 1–2 ■ Removed “Interlaken PCS Hard IP” and “10G Ethernet Hard IP” ■ ...
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... Page 22 Stratix V Device Overview Revision History December 2012 Altera Corporation ...