5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet - Page 18

• Manufacturer Part Number: 5SGXEA4H2F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4H2F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 552
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Page 18
Automatic Single Event Upset Error Detection and Correction
HardCopy V Devices
Stratix V Device Overview
You no longer need to know all the details of the FPGA architecture to perform partial
reconfiguration. Altera simplifies the process by extending the power of incremental
compilation used in earlier versions of the Quartus II software.
Partial reconfiguration is supported in the following configurations:
■
■
■
Stratix V devices offer single event upset (SEU) error detection and correction
circuitry that is robust and easy to use. The correction circuitry includes protection for
configuration RAM (CRAM) programming bits and user memories. The CRAM is
protected by a continuously running cyclical redundancy check (CRC) error detection
circuit with integrated ECC that automatically corrects one or double-adjacent bit
errors and detects higher order multi-bit errors. When more than two errors occur,
correction is available through a core programming file reload that refreshes a design
while the FPGA is operating.
The physical layout of the FPGA is optimized to make the majority of multi-bit upsets
appear as independent single- or double-adjacent bit errors, which are automatically
corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection
in Stratix V devices, user memories include integrated ECC circuitry and are layout-
optimized to enable error detection of 3-bit errors and correction for 2-bit errors.
HardCopy V ASICs offer the lowest risk and lowest total cost in ASIC designs with
embedded high-speed transceivers. You can prototype and debug with Stratix V
FPGAs, then use HardCopy V ASICs for volume production. The proven turnkey
process creates a functionally equivalent HardCopy V ASIC with or without
embedded transceivers to meet all timing constraints in as little as 12 weeks.
The powerful combination of Stratix V FPGAs and HardCopy V ASICs can help you
meet your design requirements. Whether you plan for ASIC production and require
the lowest-risk, lowest-cost path from specification to production or require a cost
reduction path for your FPGA-based systems, Altera provides the optimal solution
for power, performance, and device bandwidth.
Partial reconfiguration through the FPP x16 I/O interface
CvP
Soft internal core, such as the Nios
®
II processor.
Automatic Single Event Upset Error Detection and Correction
December 2012 Altera Corporation