5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet - Page 19

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5SGXEA4H2F35I3LN

Manufacturer Part Number
5SGXEA4H2F35I3LN
Description
FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
Manufacturer
Altera Corporation
Series
Stratix V GXr
Datasheet

Specifications of 5SGXEA4H2F35I3LN

Rohs
yes
Number Of Logic Blocks
1900
Number Of I/os
552
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FBGA-1152
Distributed Ram
37 Mbit
Minimum Operating Temperature
- 40 C
Ordering Information
Ordering Information
Figure 2. Ordering Information for Stratix V Devices
December 2012 Altera Corporation
Note to
(1) You can select one or both of these options, or you can ignore these options.
Family Signature
5S : Stratix V
Figure
Family Variant
GX : 14.1-Gbps transceivers
GT : 28.05-Gbps transceivers
GS: DSP-Oriented
E:
Embedded HardCopy
Block Variant
M : Mainstream
E : Extended
no transceivers
Highest logic density,
2:
Member Code
GX GT GS
A3
A4
A5
A7
A9
AB
B5
B6
B9
BB
C5
C7
This section describes ordering information for Stratix V GT, GX, GS, and E devices.
Figure 2
D3
D4
D5
D6
D8
5S
E9
EB
E
shows the ordering codes for Stratix V devices.
GX
M
Transceiver PMA
Speed Grade
1 (fastest)
2
3
Transceiver Count
E : 12
H : 24
K : 36
N : 48
R : 66
A5
K
3
Ball Array Dimension
Corresponds to pin count
29 : 780 pins
35 : 1,152 pins
40 : 1,517 pins
43 : 1,760 pins
45 : 1,932 pins
F
Package Type
F : FineLine BGA
H : Hybrid FineLine BGA
35
C
2
Operating Temperature
C : Commercial (0 to 85 ° C)
I
: Industrial (–40 to 100°C)
L N ES
Transceiver PCS and
FPGA Fabric Speed Grade
1 (fastest)
2
3
4
Optional Suffix (1)
L : Low-power device
N : Lead-free packaging
ES : Engineering sample silicon
Stratix V Device Overview
Page 19

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