5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet - Page 14

• Manufacturer Part Number: 5SGXEA4H2F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4H2F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 552
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Page 14
Clocking
Fractional PLL
Embedded Memory
Stratix V Device Overview
The Stratix V device core clock network is designed to support 717-MHz fabric
operations and 1,066-MHz and 1,600-Mbps external memory interfaces. The clock
network architecture is based on Altera’s proven global, quadrant, and peripheral
clock structure, which is supported by dedicated clock input pins and fractional clock
synthesis PLLs. The Quartus II software identifies all unused sections of the clock
network and powers them down, which reduces power consumption.
Stratix V devices have up to 32 fractional PLLs that you can use to reduce both the
number of oscillators required on the board and the clock pins used in the FPGA by
synthesizing multiple clock frequencies from a single reference clock source. In
addition, you can use the fractional PLLs for clock network delay compensation, zero
delay buffering, and transmitter clocking for transceivers. Fractional PLLs can be
individually configured for integer mode or fractional mode with third-order
delta-sigma modulation.
Stratix V devices contain two types of embedded memory blocks: MLAB (640-bit) and
M20K (20-Kbit). MLAB blocks are ideal for wide and shallow memories. M20K blocks
are useful for supporting larger memory configurations and include ECC. Both types
operate up to 600 MHz and can be configured to be a single- or dual-port RAM, FIFO,
ROM, or shift register. These memory blocks are flexible and support a number of
memory configurations, as shown in
Table 9. Embedded Memory Block Configuration
The Quartus II software simplifies design re-use by automatically mapping memory
blocks from legacy Stratix devices into the Stratix V memory architecture.
MLAB (640 Bits)
32x20
64x10
Table
9.
M20K (20,480 Bits)
December 2012 Altera Corporation
512x40
1Kx20
2Kx10
16Kx1
4Kx5
8Kx2
Clocking