5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet - Page 12

• Manufacturer Part Number: 5SGXEA4H2F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4H2F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 552
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Page 12
Table 7. Transceiver PCS Features (Part 2 of 2)
PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
Stratix V Device Overview
x1, x4, x8 PCIe
Gen3
10G Ethernet
Interlaken
40GBASE-R
Ethernet
100GBASE-R
Ethernet
OTN 40 and 100
GbE
XAUI
SRIO
CPRI
GPON
Protocol
Data Rates (Gbps)
1.25, 2.5, and 10
Stratix V devices have PCIe hard IP designed for performance, ease-of-use, and
increased functionality. The PCIe hard IP consists of the PCS, data link, and
transaction layers. The PCIe hard IP supports Gen3, Gen2, and Gen1 end point and
root port up to x8 lane configurations.
The Stratix V PCIe hard IP operates independently from the core logic, which allows
the PCIe link to wake up and complete link training in less than 100 ms while the
Stratix V device completes loading the programming file for the rest of the FPGA. The
PCIe hard IP also provides added functionality, which helps support emerging
features such as Single Root I/O Virtualization (SR-IOV) or optional protocol
extensions. In addition, the Stratix V device PCIe hard IP has improved end-to-end
data path protection using ECC and enables device CvP.
In all Stratix V devices, the primary PCIe hard IP that supports CvP is always in the
bottom left corner of the device (IOBANK_B0L) when viewing the die from the top.
4.9 to 10.3125
0.6144 to 9.83
(10 +1) x 11.3
3.125 to 4.25
10 x 10.3125
(4 +1) x 11.3
1.25 to 6.25
4 x 10.3125
10.3125
1.25
8
Phase compensation FIFO, encoder,
scrambler, gear box, and bit slip
TX FIFO, 64/66 encoder, scrambler,
and gear box
TX FIFO, frame generator, CRC-32
generator, scrambler, disparity
generator, and gear box
TX FIFO, 64/66 encoder, scrambler,
alignment marker insertion, gearbox,
and block striper
TX FIFO, channel bonding, and byte
serializer
Same as custom PHY plus GbE state
machine
Same as custom PHY plus XAUI state
machine for bonding four channels
Same as custom PHY plus SRIO V2.1
compliant x2 and x4 channel bonding
Same as custom PHY plus TX
deterministic latency
Same as custom PHY
Transmitter Data Path
PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
Block synchronization, rate match
FIFO, decoder, de-scrambler, and
phase compensation FIFO
RX FIFO, 64/66 decoder, de-
scrambler, block synchronization, and
gear box
RX FIFO, frame generator, CRC-32
checker, frame decoder, descrambler,
disparity checker, block
synchronization, and gearbox
RX FIFO, 64/66 decoder, de-
scrambler, lane reorder, deskew,
alignment marker lock, block
synchronization, gear box, and
destripper
RX FIFO, lane deskew, and byte de-
serializer
Same as custom PHY plus GbE state
machine
Same as custom PHY plus XAUI state
machine for re-aligning four channels
Same as custom PHY plus SRIO
V2.1-compliant x2 and x4 deskew
state machine
Same as custom PHY plus RX
deterministic latency
Same as custom PHY
December 2012 Altera Corporation
Receiver Data Path