5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet - Page 2

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5SGXEA4H2F35I3LN

Manufacturer Part Number
5SGXEA4H2F35I3LN
Description
FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
Manufacturer
Altera Corporation
Series
Stratix V GXr
Datasheet

Specifications of 5SGXEA4H2F35I3LN

Rohs
yes
Number Of Logic Blocks
1900
Number Of I/os
552
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FBGA-1152
Distributed Ram
37 Mbit
Minimum Operating Temperature
- 40 C
Page 2
Stratix V Device Overview
Stratix V E devices offer the highest logic density within the Stratix V family with
nearly one million logic elements (LEs) in the largest device. These devices are
optimized for applications such as ASIC and system emulation, diagnostic imaging,
and instrumentation.
Common to all Stratix V family variants are a rich set of high-performance building
blocks, including a redesigned adaptive logic module (ALM), 20 Kbit (M20K)
embedded memory blocks, variable precision DSP blocks, and fractional
phase-locked loops (PLLs). All of these building blocks are interconnected by Altera’s
superior multi-track routing architecture and comprehensive fabric clocking network.
Also common to Stratix V devices is the new Embedded HardCopy Block, which is a
customizable hard IP block that leverages Altera’s unique HardCopy ASIC
capabilities. The Embedded HardCopy Block in Stratix V FPGAs is used to harden IP
instantiation of PCIe Gen3, Gen2, and Gen1.
December 2012 Altera Corporation
Stratix V Family Variants

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