5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet - Page 13

• Manufacturer Part Number: 5SGXEA4H2F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4H2F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 552
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

External Memory and GPIO
External Memory and GPIO
Adaptive Logic Module
December 2012 Altera Corporation
Each Stratix V I/O block has a hard FIFO that improves the resynchronization margin
as data is transferred from the external memory to the FPGA. The hard FIFO also
lowers PHY latency, resulting in higher random access performance. GPIOs include
on-chip dynamic termination to reduce the number of external components and
minimize reflections. On-package decoupling capacitors suppress noise on the power
lines, which reduce noise coupling into the I/Os. Memory banks are isolated to
prevent core noise from coupling to the output, thus reducing jitter and providing
optimal signal integrity.
The external memory interface block uses advanced calibration algorithms to
compensate for process, voltage and temperature (PVT) variations in the FPGA and
external memory components. The advanced algorithms ensure maximum
bandwidth and a robust timing margin across all conditions. Stratix V devices deliver
a complete memory solution with the High Performance Memory Controller II
(HPMC II) and UniPHY MegaCore
memory modules.
Table 8. External Memory Interface Performance
Stratix V devices use an improved ALM to implement logic functions more efficiently.
The Stratix V ALM has eight inputs with a fracturable look-up table (LUT), two
dedicated embedded adders, and four dedicated registers.
The Stratix V ALM has the following enhancements:
■
■
■
The Quartus II software leverages the Stratix V ALM logic structure to deliver the
highest performance, optimal logic usage, and lowest compile times. The Quartus II
software simplifies design re-use because it automatically maps legacy Stratix designs
into the new Stratix V ALM architecture.
Note to
(1) The specifications listed in this table are performance targets. For a current achievable performance, use the
Packs 6% more logic when compared with the ALM found in Stratix IV devices
Implements select 7-input LUT-based functions, all 6-input logic functions, and
two independent functions consisting of smaller LUT sizes (such as two
independent 4-input LUTs) to optimize core usage
Adds more registers (four registers per 8-input fracturable LUT). More registers
allow Stratix V devices to maximize core performance at a higher core logic usage
and provides easier timing closure for register-rich and heavily pipelined designs.
External Memory Interface Spec
Table
8:
RLDRAM III
RLDRAM II
Interface
QDR II+
QDR II
Table 8
DDR3
DDR2
lists external memory interface block performance.
Estimator.
®
IP that simplifies a design for today’s advanced
(1)
Performance (MHz)
1,066
533
350
550
533
800
Stratix V Device Overview
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