5SGXEA4H2F35I3LN Altera Corporation, 5SGXEA4H2F35I3LN Datasheet - Page 3

• Manufacturer Part Number: 5SGXEA4H2F35I3LN
• Description: FPGA - Field Programmable Gate Array FPGA - Stratix V GX 1900 LABS 552 IOs
• Manufacturer: Altera Corporation
• Series: Stratix V GXr

Specifications of 5SGXEA4H2F35I3LN

• Rohs: yes
• Number Of Logic Blocks: 1900
• Number Of I/os: 552
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-1152
• Distributed Ram: 37 Mbit
• Minimum Operating Temperature: - 40 C

Stratix V Features Summary
Stratix V Features Summary
December 2012 Altera Corporation
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Technology
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Low-power serial transceivers
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General-purpose I/Os (GPIOs)
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Embedded HardCopy Block
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Embedded transceiver hard IP
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Power Management
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High-performance core fabric
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28-nm TSMC process technology
0.85-V or 0.9-V core voltage
28.05-Gbps transceivers on Stratix V GT devices
Electronic dispersion compensation (EDC) for XFP,
SFP+, QSFP, CFP optical module support
Adaptive linear and decision feedback equalization
600-Megabits per second (Mbps) to 14.1-Gbps
backplane capability
Transmitter pre-emphasis and de-emphasis
Dynamic reconfiguration of individual channels
On-chip instrumentation (EyeQ non-intrusive data eye
monitoring)
1.4-Gbps LVDS
1,066-MHz external memory interface
On-chip termination (OCT)
1.2-V to 3.3-V interfacing for all Stratix V devices
PCIe Gen3, Gen2, and Gen1 complete protocol stack,
x1/x2/x4/x8 end point and root port
Interlaken physical coding sublayer (PCS)
Gigabit Ethernet (GbE) and XAUI PCS
10G Ethernet PCS
Serial RapidIO
Common Public Radio Interface (CPRI) PCS
Gigabit Passive Optical Networking (GPON) PCS
Programmable Power Technology
Quartus II integrated PowerPlay Power Analysis
Enhanced ALM with four registers
Improved routing architecture reduces congestion and
improves compile times
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(SRIO) PCS
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Embedded memory blocks
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Variable precision DSP blocks
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Fractional PLLs
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Clock networks
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Device Configuration
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High-performance packaging
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HardCopy V migration
M20K: 20-Kbit with hard error correction code (ECC)
MLAB: 640-bit
Up to 500 MHz performance
Natively support signal processing with precision
ranging from 9x9 up to 54x54
New native 27x27 multiply mode
64-bit accumulator and cascade for systolic finite
impulse responses (FIRs)
Embedded internal coefficient memory
Pre-adder/subtractor improves efficiency
Increased number of outputs allows more independent
multipliers
Fractional mode with third-order delta-sigma
modulation
Integer mode
Precision clock synthesis, clock delay compensation,
and zero delay buffer (ZDB)
717-MHz fabric clocking
Global, quadrant, and peripheral clock networks
Unused clock networks can be powered down to
reduce dynamic power
Serial and parallel flash interface
Enhanced advanced encryption standard (AES) design
security features
Tamper protection
Partial and dynamic reconfiguration
Configuration via Protocol (CvP)
Multiple device densities with identical package
footprints enables seamless migration between
different FPGA densities
FBGA packaging with on-package decoupling
capacitors
Lead and RoHS-compliant lead-free options
Stratix V Device Overview
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