S29GL256S90DHI023 Spansion, S29GL256S90DHI023 Datasheet
S29GL256S90DHI023
Specifications of S29GL256S90DHI023
Related parts for S29GL256S90DHI023
S29GL256S90DHI023 Summary of contents
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... S29GL128S 128 Mbit CMOS 3.0 Volt Core with Versatile I/O Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S29GL_128S_01GS_00 ® ...
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... The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “ ...
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... Publication Number S29GL_128S_01GS_00 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com- binations offered may occur. ™ ...
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Performance Summary Density 128 Mb 256 Mb 512 Buffer Programming (512 bytes) Sector Erase (128 kbytes) Active Read at 5 MHz Maximum Read Access Times ...
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... Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5 Error Types and Clearing Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6 Embedded Algorithm Performance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6. Software Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1 Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 Device ID and Common Flash Interface (ID-CFI) ASO Map . . . . . . . . . . . . . . . . . . . . . . . . . 60 Hardware Interface 7. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1 Address and Data Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2 Input/Output Summary 7.3 Versatile I/O Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.4 Ready/Busy# (RY/BY 7.5 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8 ...
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... FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12. Special Handling Instructions for FBGA Package 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14. Other Resources 100 14.1 Links to Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.2 Links to Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.3 Specification Bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.4 Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ® GL-S MirrorBit Family S29GL_128S_01GS_00_07 December 21, 2012 ...
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Figures Figure 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tables Table 1.1 S29GL-S Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 10.7 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... MAX The GL-S family combines the best features of eXecute In Place (XIP) and Data Storage flash memories. This family has the fast random access of XIP flash along with the high density and fast program speed of Data Storage flash. Read access to any random location takes 120 ns depending on device density and I/O power supply voltage ...
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... The erased state of each memory bit is a logic 1. Programming changes a logic 1 (High logic 0 (Low). Only an Erase operation is able to change erase operation must be performed on an entire 128-kbyte aligned and length group of data call a Sector. When shipped from Spansion all Sectors are erased. ...
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... Flash Memory Array: the main non-volatile memory array used for storage of data that may be randomly accessed by asynchronous read operations. ID/CFI: a memory array used for Spansion factory programmed device characteristics information. This area contains the Device Identification (ID) and Common Flash Interface (CFI) information tables. ...
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... When an Embedded Algorithm is suspended, the Data Polling ASO is visible until the device has suspended the EA. When the EA is suspended the Data Polling ASO is exited and Flash Array data is available. The Data Polling ASO is reentered when the suspended EA is resumed, until the EA is again suspended or finished ...
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... Autoselect (ID) or CFI overlay will cause the now combined ID-CFI address map to appear. The ID-CFI address map appears within, and overlays the Flash Array data of, the sector selected by the address used in the ID-CFI enter command. While the ID-CFI ASO is entered the content of all other sectors is undefined ...
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... The original industry format made the high order byte always 0. Spansion has modified the format to use both bytes in some words of the address space. For the detail description of the Device ID address map see 2 ...
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... Secure Silicon Region ASO The Secure Silicon Region (SSR) provides an extra flash memory area that can be programmed once and permanently protected from further changes One Time Program (OTP) area. The SSR is 1024 bytes in length. It consists of 512 bytes for Factory Locked Secure Silicon Region and 512 bytes for Customer Locked Secure Silicon Region ...
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... Persistent Protection Bits (PPB) ASO The PPB ASO contains one bit of a Flash Memory Array for each Sector in the device. When the PPB ASO is entered, the PPB bit for a sector appears in the Least Significant Bit (LSB) of each address in the sector. Reading any address in a sector displays data where the LSB indicates the non-volatile protection status for that sector ...
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... Secure Silicon Region (OTP) The Secure Silicon Region (SSR) provides an extra flash memory area that can be programmed once and permanently protected from further changes One Time Program (OTP) area. The SSR is 1024 bytes in length. It consists of 512 bytes for Factory Locked Secure Silicon Region and 512 bytes for Customer Locked Secure Silicon Region ...
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... Sector Highest Address Sector. Every main flash array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it. When either bit is 0, the sector is protected from program and erase operations. The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for managing the state of the PPB Lock bit, Persistent Protection and Password Protection ...
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... The Lock Register also contains OTP bits, for protecting the SSR. The PPB bits are erased so that all main flash array sectors are unprotected when shipped from Spansion. The Secured Silicon Region can be factory protected or left unprotected depending on the ordering option (model) ordered ...
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Sector Protection States Summary Each sector can be in one of the following protection states: Unlocked – The sector is unprotected and protection can be changed by a simple command. The protection state defaults to unprotected after a ...
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... Password Protection Notes: The Password Program Command is only capable of programming 0’s. The password is all 1’s when shipped from Spansion located in its own memory space and is accessible through the use of the Password Program and Password Read commands. All 64-bit password combinations are valid as a password. ...
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... The specific address and data are compared after the Program Buffer To Flash command has been given. If they don't match to the internal set value than the status register will return to the ready state with the Program Status Bit set to 1 and Program Status Register Bit set to 1 indicating a failed programming operation ...
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Read Operations 4.1 Asynchronous Read Each read access may be made to any location in the memory (random access). Each random access is self- timed with the same latency from CE# or address to valid data (t 4.2 Page ...
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... Algorithm Controller (EAC). The main algorithms perform programming and erasing of the main array data and the ASO’s. The host system writes command codes to the flash device address space. The EAC receives the commands, performs all the necessary steps to complete the command, and provides status information during the progress ...
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... Flash data bits are erased in parallel in a large group called a sector. The Erase operation places each data bit in the sector in the logical 1 state (High). Flash data bits may be individually programmed from the erased 1 state to the programmed logical 0 (low) state. A data bit of 0 cannot be programmed back succeeding read shows that the data is still 0 ...
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... Program Methods 5.3.1.1 Word Programming Word programming is used to program a single word anywhere in the main Flash Memory Array. The Word Programming command is a four-write-cycle sequence. The program command sequence is initiated by writing two unlock write cycles, followed by the program set up command. The program address and data are written next, which in turn initiate the Embedded Word Program algorithm ...
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... If an incorrect number of write buffer locations have been loaded the operation will abort and return to the initiating state. The abort occurs when anything other than the Program Buffer to Flash is written when that command is expected at the end of the word count. ...
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... Write Starting Address/Data Yes Yes ABORT Write to Buffer Operation? No Write next Address/Data pair (Note Write Program Buffer to Flash Confirm, Sector Address Read DQ7-DQ0 with Addr = LAST LOADED ADDRESS DQ7 = Data DQ5 = 1? Yes Yes Read DQ7-DQ0 with Addr = LAST LOADED ADDRESS ...
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... Sector Address Write Starting Address/Data Yes Yes ABORT Write to Buffer Operation? No Write next Address/Data pair (Note Write Program Buffer to Flash Confirm, Sector Address Read Status Register Yes DRB SR[ Yes PSB SR[ Program Fail WBASB Yes ...
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Sequence Issue Unlock Command 1 Issue Unlock Command 2 Issue Write to Buffer Command at Sector Address Issue Number of Locations at Sector Address Example words to pgm words to ...
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... Chip Erase The chip erase function erases the entire main Flash Memory Array. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all 0 data pattern prior to electrical erase. After a successful chip erase, all locations within the device contain FFFFh ...
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Sector Erase The sector erase function erases one sector in the memory array. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire sector for an all ...
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... The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main flash array. This command is valid only during sector erase or program operation. The Erase Suspend command is ignored if written during the chip erase operation. ...
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... ID-CFI ASO again with the new SA. ASO Exit. The following source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion flash memory software development guidelines. ...
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Lock Register ASO The system can access the Lock Register by issuing the Lock Register entry command sequence during Read Mode. This entry command does not use a sector address from the entry command. The Lock Register appears at ...
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... There is no software reset latency requirement. The reset command is executed during the t 5.4 Status Monitoring There are three methods for monitoring EA status. Previous generations of the S29GL flash family used the methods called Data Polling and Ready/Busy# (RY/BY#) Signal. These methods are still supported by the S29GL-S family. One additional method is reading the Status Register. ...
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Program Suspended (bit 2), The current state bits indicate whether process, suspended, or completed. The upper 8 bits (bits 15:8) are reserved. These have undefined High or Low value that can change from one status ...
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DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or has completed. Data# Polling is valid after the rising edge of the final WE# pulse in the program ...
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Program Suspend or Erase Suspend mode. Toggle Bit I may ...
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... When a timeout occurs, the software must send a reset command to clear the timeout bit (DQ5) and to return the EAC to read array mode. In this case possible that the flash will continue to communicate busy for µs after the reset command is sent. ...
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... If an erase was suspended before the error the device returns to the erase suspended state awaiting flash array read or a command write. Otherwise, the device will be in standby state awaiting flash array read or a command write Table 5 ...
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Embedded Operation Error If an error occurs during an embedded operation (program, erase, blank check, or password unlock) the device (EAC) remains busy. The RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, ...
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... When the busy period ends the device returns to normal operation, the data polling status is no longer overlaid, RY/BY# is High, and the status register shows ready with valid status bits. The device is ready for flash array read or write of a new command. After the protection error status busy period the Status Register will show the following: ...
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Write Buffer Abort If an error occurs during a Write to Buffer command the device (EAC) remains busy. The RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, and the status register shows ...
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Embedded Algorithm Performance Table Parameter Sector Erase Time 128 kbyte Single Word Programming Time Buffer Programming Time Effective Write Buffer Program Operation per Word Sector Programming Time 128 kB (full Buffer Programming) Erase Suspend/Erase Resume (t Program Suspend/Program Resume ...
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Parameter Sector Erase Time 128 kbyte Single Word Programming Time Buffer Programming Time Effective Write Buffer Program Operation per Word Sector Programming Time 128 kB (full Buffer Programming) Erase Suspend/Erase Resume (t Program Suspend/Program Resume (t Erase Resume to next ...
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Command State Transitions Command Current State Read and Condition Address RA Data RD - READ READ Read Protect = False READSR - (return) Table 5.7 Read Unlock Command State Transition Status Command Current Register and Read State Read Condition ...
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Table 5.9 Erase Suspend State Command Transition Command and Current State Condition Address Data ESR (1) - SR( SR( ESSR - Note: 1. State will automatically move to ES state by t ESL Table 5.10 ...
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Table 5.12 Erase Suspend - Program Command State Transition Current State Command Read and Condition Address RA Data RD WC > 256 or SA ≠ SA ES_WB ES_WB WC ≤ 256 and < Write ...
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... Status Register Status Register Read Read Enter Clear RA x555h x555h RD x70h x71h PSR PGSR (PSR PSSR (PS) PS (return ® GL-S MirrorBit Family Program Erase Program Buffer to Suspend Suspend flash Enhanced Enhanced (confirm) Method (2) Method (SA) x29h xB0h x51h - - - - - - PSR (PG) PSR (PG NOT a valid “ ...
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Table 5.17 Lock Register State Command Transition Command Current State and Read Condition Address RA Data LRPG1 - LRPG1 LRPG - LRPG LRSR - (return) LREXT - LREXT Command and Current State Condition Address Data CFI ...
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Table 5.21 Secure Silicon Sector Program State Command Transition Command and Current State Condition Address Data SSRPG1 - WC > 256 or SA ≠ SA SSR_WB WC ≤ 256 and < Write Buffer ≠ ...
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Table 5.23 Non-Volatile Protection Command State Transition Command Software Current and Read Reset / State Condition ASO Exit Address RA xh Data RD xF0h PPB - PPB READ PPBPG1 - PPBPG1 READ SR( PPBPG PPBPG SR(7) = ...
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Current State Command Transition BLCK Table 5.8 CER Table 5.8 CFI Table 5.18 CFISR Table 5.18 DYB Table 5.25 DYBEXT Table 5.25 DYBSET Table 5.25 DYBSR Table 5.25 ER Table 5.8 ERSR Table 5.8 ERUL1 Table 5.8 ERUL2 Table 5.8 ...
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Current State Command Transition PPBPG1 Table 5.23 PPBSR Table 5.23 PPD Table 5.22 PPEXT Table 5.22 PPPG Table 5.22 PPPG1 Table 5.22 PPSR Table 5.22 PS Table 5.16 PSR Table 5.16 PSSR Table 5.16 PPWB25 Table 5.22 READ Table 5.6 ...
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... Reset/ASO Exit 1 XXX F0 (Notes 7, 16) SSR Entry 3 555 AA Read (Note Word Program 4 555 AA Write to Buffer 6 555 AA Program Buffer to Flash (confirm) Write-to-Buffer-Abort 3 555 AA Reset (Note 11) SSR Exit (Note 11) 4 555 AA Reset/ASO Exit 1 XXX F0 (Notes 7, 16) December 21, 2012 S29GL_128S_01GS_00_07 ...
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Command Sequence First (Note 1) Addr Data Lock Register Entry 3 555 Program (Note 15) 2 XXX Read (Note 15 Command Set Exit 2 XXX (Notes 12, 16) Reset/ASO Exit 1 XXX (Notes 7, 16) Password ASO Entry ...
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Command Sequence First (Note 1) Addr Data DYB ASO Entry 3 555 AA DYB Set (Note 17) 2 XXX A0 DYB Clear (Note 17) 2 XXX A0 DYB Status Read (0) (Note 17) Command Set Exit 2 ...
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... Device ID and Common Flash Interface (ID-CFI) ASO Map The Device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, Sector Protection State, and basic feature set information for the device. ID-CFI Location 02h displays sector protection status for the sector selected by the sector address (SA) used in the ID-CFI enter command ...
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Word Address (SA) + 0010h (SA) + 0011h (SA) + 0012h (SA) + 0013h (SA) + 0014h (SA) + 0015h (SA) + 0016h (SA) + 0017h (SA) + 0018h (SA) + 0019h (SA) + 001Ah Word Address (SA) + 001Bh ...
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... Gb) 001Ah (512 Mb) N Device Size = 2 byte; 0019h (256 Mb) 0018h (128 Mb) 0001h Flash Device Interface Description 0 = x8-only x16-only x8/x16 capable 0000h 0009h Max. number of byte in multi-byte write = 2 (00 = not supported) 0000h Number of Erase Block Regions within device 0001h 1 = Uniform Device Boot Device ...
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Table 6.6 CFI Primary Vendor-Specific Extended Query (Sheet Word Address (SA) + 0040h (SA) + 0041h (SA) + 0042h (SA) + 0043h (SA) + 0044h (SA) + 0045h (SA) + 0046h (SA) + 0047h (SA) + 0048h ...
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... Data WP# Protection 00h = Flash device without WP Protect (No Boot) 01h = Eight 8 kB Sectors at TOP and Bottom with WP (Dual Boot) 02h = Bottom Boot Device with WP Protect (Bottom Boot) 0004h (Bottom) 03h = Top Boot Device with WP Protect (Top Boot) ...
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... Reserved for Future Use. Not currently connected internally but the pin/ball location should be left unconnected and unused by PCB routing channel for future compatibility. The pin/ball may be used by a signal in the future. Do Not Use. Reserved for use by Spansion. The pin/ball is connected internally. The input has an internal pull down resistance to V the PCB. ...
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Ready/Busy# (RY/BY#) RY/BY dedicated, open drain output pin that indicates whether an Embedded Algorithm, Power-On Reset (POR), or Hardware Reset is in progress or complete. The RY/BY# status is valid after the rising edge of the final ...
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... Signal Protocols The following sections describe the host system interface signal behavior and timing for the 29GL-S family flash devices. 8.1 Interface States Table 8.1 describes the required value of each interface signal for each interface state. Interface State Power-Off with Hardware Data Protection ...
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Power Conservation Modes 8.3.1 Interface Standby Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CE# = High). All inputs are ignored in this state and ...
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Random (Asynchronous) Read When the host system interface selects the memory device by driving CE# Low, the device interface leaves the Standby state. If WE# is High when CE# goes Low, a random read access is started. The data ...
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Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on WE# will not initiate a write cycle. 8.5.3 Logical Inhibit Write cycles are inhibited by holding OE and WE# must be Low (V 70 ...
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Electrical Specifications 9.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground All pins other than RESET# RESET# (Note 1) Output Short Circuit Current Notes: 1. Minimum ...
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Symbol V V Power Supply level below which re-initialization is required LKO and V RST and V VCS CC t Duration Note: 1. Not 100% tested. P ...
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Input Signal Overshoot V December 21, 2012 S29GL_128S_01GS_00_07 Figure 9.3 Maximum Negative Overshoot Waveform max IL V min IL – Figure 9.4 ...
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DC Characteristics Parameter Description I Input Load Current LI I Output Leakage Current Active Read Current CC1 Intra-Page Read Current CC2 CC V Active Erase/Program CC I CC3 Current (Notes ...
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Parameter Description I Input Load Current LI I Output Leakage Current Active Read Current CC1 Intra-Page Read Current CC2 CC V Active Erase/Program CC I CC3 Current (Notes Standby Current ...
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Capacitance Characteristics Parameter Symbol OUT C IN2 RY/BY# Notes: 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A Parameter Symbol OUT C IN2 RY/BY# Notes: 1. ...
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Timing Specifications 10.1 Key to Switching Waveforms Waveform 10.2 AC Test Conditions Output Load Capacitance, C Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Note: 1. Measured between V ...
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Power-On Reset (POR) and Warm Reset Normal precautions must be taken for supply decoupling to stabilize the V device in a system should have the V the package connections (this capacitor is generally on the order of 0.1 µF). ...
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Hardware (Warm) Reset During Hardware Reset (t When RESET# continues to be held at V held but not Cold Reset has not been completed by the device when RESET# is asserted ...
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AC Characteristics 10.4.1 Asynchronous Read Operations Table 10.3 Read Operation V Parameter JEDEC Std t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t ...
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Table 10.5 Read Operation V Parameter JEDEC Std t t Read Cycle Time AVAV Address to Output Delay AVQV ACC Chip Enable to Output t t ELQV CE Delay t Page Access Time PACC t t Output ...
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Amax-A0 CE# OE# DQ15-DQ0 Amax-A0 CE# OE# DQ15-DQ0 Note: Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access. Amax-A4 A3-A0 CE# OE# DQ15-DQ0 Note: Word Configuration: Toggle A0, A1, ...
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Asynchronous Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t OEPH t t GHWL GHWL t t ELWL ...
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Figure 10.9 Back to Back (CE#VIL) Write Operation Timing Diagram Amax-A0 WE# DQ15-DQ0 Amax-A0 CE# OE# WE# DQ15-DQ0 tWC tAS tAH tCS CE# OE# tWP tDS Figure 10.10 Write to ...
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Amax-A0 CE# OE# WE# DQ15-DQ0 Amax-A0 CE# OE# WE# DQ15-DQ0 December 21, 2012 S29GL_128S_01GS_00_07 Figure 10.11 Write to Read (t ) Operation Timing Diagram CE tAH tAS tSR_W tCS tCH tOEH ...
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Figure 10.13 Read to Write (CE# Toggle) Operation Timing Diagram Amax-A0 CE# OE# WE# DQ15-DQ0 Parameter JEDEC Std t t WHWH1 WHWH1 t t WHWH2 WHWH2 t BUSY t SR/W t ESL t PSL t RB Notes: 1. Not 100% ...
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Addresses CE# OE# WE# Data RY/BY# Note program address program data, D Addresses CE# OE# WE# Data RY/BY# Note sector address (for sector erase valid address for reading status data. ...
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Figure 10.16 Data# Polling Timing Diagram (During Embedded Algorithms) Addresses CE OE# WE# DQ7 DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array ...
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Alternate CE# Controlled Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t CEPH t 0EPH t t GHEK ...
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Amax-A0 CE# OE# WE# DQ15-DQ0 Figure 10.20 (CE#) Write to Read Operation Timing Diagram tWC tAS tAH tOEH tWS tWH tDH tDS ® GL-S MirrorBit Family tACC tCE tDF tOE ...
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... DNU Notes: 1. Pin 28, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Do not use these connections for PCB Signal routing channels. Though not recommended, the ball can be connected ...
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Physical Diagram Figure 11.2 56-Pin Thin Small Outline Package (TSOP PACKAGE JEDEC MO-142 (B) EC SYMBOL MIN. A --- A1 0.05 A2 0.95 b1 0.17 b 0.17 c1 0.10 c 0.10 D 19.80 D1 18.30 ...
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... NC Notes: 1. Ball E1, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Do not use these connections for PCB Signal routing channels. Though not recommended, the ball can be connected ...
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Physical Diagram – LAE064 Figure 11.4 LAE064—64-ball Fortified Ball Grid Array (FBGA PACKAGE LAE 064 JEDEC N/A 9. 9.00 mm PACKAGE SYMBOL MIN NOM A --- A1 0.40 A2 0.60 D 9.00 BSC. ...
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Physical Diagram – LAA064 PACKAGE LAA 064 JEDEC N/A 13. 11.00 mm PACKAGE SYMBOL MIN NOM A --- --- A1 0.40 --- A2 0.60 --- D 13.00 BSC. E 11.00 BSC. D1 7.00 BSC. E1 7.00 BSC. ...
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... Notes: 1. Ball G1, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Spansion test or other purposes and is not intended for connection to any host system signal. Do not use these connections for PCB Signal routing channels. Though not recommended, the ball can be connected ...
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... Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. ...
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Ordering Information Valid Combinations The Recommended Combinations table lists configurations planned to be available in volume. The table below will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and ...
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... G = Fortified Ball-Grid Array Package (VBU056 Thin Small Outline Package (TSOP) Standard Pinout Speed Option random access time 10 = 100 ns random access time 11 = 110 ns random access time 12 = 120 ns random access time Option, 1024, 512, 256, 128 Megabit Page-Mode Flash Memory, IO ® GL-S MirrorBit Family and V Range) ...
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... VHDL and Verilog IBIS ORCAD 14.2 Links to Application Notes The following is a sample list of application notes related to this product. All Spansion application notes are available at http://www.spansion.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx Common Flash Interface Version 1.5 Vendor Specific Extensions Common Flash Memory Interface Specification ...
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... Specification Bulletins Contact your local sales office for details. 14.4 Contacting Spansion Obtain the latest list of company locations and contact information on our web site at http://www.spansion.com/About/Pages/Locations.aspx December 21, 2012 S29GL_128S_01GS_00_07 ® GL-S MirrorBit Family 101 ...
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... Corrected table: Non-Volatile Protection Command State Transition Corrected table: PPB Lock Bit Command State Transition Corrected table: Volatile Sector Protection Command State Transition Device ID and Common Flash Interface Corrected table: Corrected CFI Primary Vendor-Specific Extended Query description for Word (ID-CFI) ASO Map ...
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... Write Buffer Abort Added clarification Performance Table Updated Embedded Algorithm Characteristics (-40°C to +105°C) table Updated CFI Device Geometry Definition table Device ID and Common Flash Interface (ID-CFI) ASO Map Updated CFI Primary Vendor-Specific Extended Query table Asynchronous Read Operations Added Read Operation V ...
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... Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure ...