S29GL256S90DHI023 Spansion, S29GL256S90DHI023 Datasheet - Page 22

• Manufacturer Part Number: S29GL256S90DHI023
• Description: Flash 256M, 3V, 90ns Parallel NOR Flash
• Manufacturer: Spansion

Specifications of S29GL256S90DHI023

• Rohs: yes
• Data Bus Width: 16 bit
• Memory Type: NOR Flash
• Memory Size: 256 Mbit
• Architecture: Eclipse
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 90 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 60 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-64
• Organization: 128 KB x 128

22
3.4.8
3.4.9
3.4.9.1
Persistent Protection Mode
Password Protection Mode
If both lock bits are selected to be programmed at the same time, the operation will abort. Once the Password
Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled and no changes to the
protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode
is permanently disabled.
If the password mode is to be chosen, the password must be programmed prior to setting the corresponding
lock register bit. Setting the Password Protection Mode Lock Bit is programmed, a power cycle, hardware
reset, or PPB Lock Bit Set command is required to set the PPB Lock bit to 0 to protect the PPB array.
The programming time of the Lock Register is the same as the typical word programming time. During a Lock
Register programming EA, Data polling Status DQ6 Toggle Bit I will toggle until the programming has
completed. The system can also determine the status of the lock register programming by reading the Status
Register. See
The user is not required to program DQ2 or DQ1, and DQ6 or DQ0 bits at the same time. This allows the user
to lock the SSR before or after choosing the device protection scheme. When programming the Lock Bits, the
Reserved Bits must be 1 (masked).
The Persistent Protection method sets the PPB Lock to 1 during POR or Hardware Reset so that the PPB bits
are unprotected by a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB.
There is no command in the Persistent Protection method to set the PPB Lock bit to 1 therefore the PPB Lock
bit will remain at 0 until the next power-off or hardware reset.
PPB Password Protection Mode
PPB Password Protection Mode allows an even higher level of security than the Persistent Sector Protection
Mode, by requiring a 64-bit password for setting the PPB Lock. In addition to this password requirement, after
power up and reset, the PPB Lock is cleared to 0 to ensure protection at power-up. Successful execution of
the Password Unlock command by entering the entire password sets the PPB Lock to 1, allowing for sector
PPB modifications.
Password Protection Notes:
 The Password Program Command is only capable of programming 0’s.
 The password is all 1’s when shipped from Spansion. It is located in its own memory space and is
 All 64-bit password combinations are valid as a password.
 Once the Password is programmed and verified, the Password Mode Locking Bit must be set in order to
 The Password Mode Lock Bit, once programmed, prevents reading the 64-bit password on the data bus
 The Password Mode Lock Bit is not erasable.
 The exact password must be entered in order for the unlocking function to occur.
 The addresses can be loaded in any order but all 4 words are required for a successful match to occur.
 The Sector Addresses and Word Line Addresses are compared while the password address/data are
accessible through the use of the Password Program and Password Read commands.
prevent reading or modification of the password.
and further password programming. All further program and read commands to the password region are
disabled (data is read as 1's) and these commands are ignored. There is no means to verify what the
password is after the Password Protection Mode Lock Bit is programmed. Password verification is only
allowed before selecting the Password Protection mode.
loaded. If the Sector Adddress don't match than the error will be reported at the end of that write cycle. The
status register will return to the ready state with the Program Status Bit set to 1, Program Status Register
Bit set to 1, and Write Buffer Abort Status Bit set to 1 indicating a failed programming operation. It is a
failure to change the state of the PPB Lock bit because it is still protected by the lack of a valid password.
The data polling status will remain active, with DQ7 set to the complement of the DQ7 bit in the last word of
the password unlock command, and DQ6 toggling. RY/BY# will remain low.
Status Register on page 37
GL-S MirrorBit
for information on these status bits.
D a t a
®
Family
S h e e t
S29GL_128S_01GS_00_07 December 21, 2012