S29GL256S90DHI023 Spansion, S29GL256S90DHI023 Datasheet - Page 10

• Manufacturer Part Number: S29GL256S90DHI023
• Description: Flash 256M, 3V, 90ns Parallel NOR Flash
• Manufacturer: Spansion

Specifications of S29GL256S90DHI023

• Rohs: yes
• Data Bus Width: 16 bit
• Memory Type: NOR Flash
• Memory Size: 256 Mbit
• Architecture: Eclipse
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 90 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 60 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-64
• Organization: 128 KB x 128

1.
10
Product Overview
The GL-S family consists of 128-Mbit to 1Gbit, 3.0V core, Versatile I/O, non-volatile, flash memory devices.
These devices have a 16-bit (word) wide data bus and use only word boundary addresses. All read accesses
provide 16 bits of data on each bus transfer cycle. All writes take 16 bits of data from each bus transfer cycle.
:
Note:
** A
The GL-S family combines the best features of eXecute In Place (XIP) and Data Storage flash memories.
This family has the fast random access of XIP flash along with the high density and fast program speed of
Data Storage flash.
Read access to any random location takes 90 ns to 120 ns depending on device density and I/O power
supply voltage. Each random (initial) access reads an entire 32-byte aligned group of data called a Page.
Other words within the same Page may be read by changing only the low order 4 bits of word address. Each
access within the same Page takes 15 ns to 30 ns. This is called Page Mode read. Changing any of the
higher word address bits will select a different Page and begin a new initial access. All read accesses are
asynchronous.
A
MAX
Max
RESET#
**–A0
GL01GS = A25, A
WE#
WP#
OE#
V
CE#
V
V
CC
SS
IO
RY/BY#
V
MAX
CC
Command
Register
Control
State
Detector
GL512S = A24, A
GL-S MirrorBit
MAX
PGM Voltage
Figure 1.1 Block Diagram
GL256S = A23, A
Generator
Timer
D a t a
®
Family
Sector Switches
Erase Voltage
Generator
S h e e t
MAX
GL128S = A22
STB
S29GL_128S_01GS_00_07 December 21, 2012
Output Enable
Chip Enable
Logic
Y-Decoder
X-Decoder
STB
DQ15
Input/Output
Buffers
Cell Matrix
Y-Gating
Latch
Data
–
DQ0