S29GL256S90DHI023 Spansion, S29GL256S90DHI023 Datasheet - Page 69

• Manufacturer Part Number: S29GL256S90DHI023
• Description: Flash 256M, 3V, 90ns Parallel NOR Flash
• Manufacturer: Spansion

Specifications of S29GL256S90DHI023

• Rohs: yes
• Data Bus Width: 16 bit
• Memory Type: NOR Flash
• Memory Size: 256 Mbit
• Architecture: Eclipse
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 90 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 60 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-64
• Organization: 128 KB x 128

8.5
December 21, 2012 S29GL_128S_01GS_00_07
8.4.2
8.4.3
8.5.1
Write
Random (Asynchronous) Read
Page Read
Asynchronous Write
When the host system interface selects the memory device by driving CE# Low, the device interface leaves
the Standby state. If WE# is High when CE# goes Low, a random read access is started. The data output
depends on the address map mode and the address provided at the time the read access is started.
The data appears on DQ15-DQ0 when CE# is Low, OE# is Low, WE# remains High, address remains stable,
and the asynchronous access times are satisfied. Address access time (t
stable addresses to valid output data. The chip enable access time (t
data at the outputs. In order for the read data to be driven on to the data outputs the OE# signal must be Low
at least the output enable time (t
At the completion of the random access time from CE# active (t
(t
map mode. If CE# remains Low and any of the A
random read access begins. If CE# remains Low and OE# goes High the interface transitions to the Read
with Output Disable state. If CE# remains Low, OE# goes High, and WE# goes Low, the interface transitions
to the Write state. If CE# returns High, the interface goes to the Standby state. Back to Back accesses, in
which CE# remains Low between accesses, requires an address change to initiate the second access.
See
After a Random Read access is completed, if CE# remains Low, OE# remains Low, the A
signals remain stable, and any of the A3 to A0 address signals change, a new access within the same Page
begins. The Page Read completes much faster (t
When WE# goes Low after CE is Low, there is a transition from one of the read states to the Write state. If
WE# is Low before CE# goes Low, there is a transition from the Standby state directly to the Write state
without beginning a read access.
When CE# is Low, OE# is High, and WE# goes Low, a write data transfer begins. Note, OE# and WE# should
never be Low at the same time to ensure no data bus contention between the host system and memory.
When the asynchronous write cycle timing requirements are met the WE# can go High to capture the address
and data values in to EAC command memory.
Address is captured by the falling edge of WE# or CE#, whichever occurs later. Data is captured by the rising
edge of WE# or CE#, whichever occurs earlier.
When CE# is Low before WE# goes Low and stays Low after WE# goes High, the access is called a WE#
controlled Write. When WE# is High and CE# goes High, there is a transition to the Standby state. If CE#
remains Low and WE# goes High, there is a transition to the Read with Output Disable state.
When WE# is Low before CE# goes Low and remains Low after CE# goes High, the access is called a CE#
controlled Write. A CE# controlled Write transitions to the Standby state.
If WE# is Low before CE# goes Low, the write transfer is started by CE# going Low. If WE# is Low after CE#
goes High, the address and data are captured by the rising edge of CE#. These cases are referred to as CE#
controlled write state transitions.
Write followed by Read accesses, in which CE# remains Low between accesses, requires an address
change to initiate the following read access.
Back to Back accesses, in which CE# remains Low between accesses, requires an address change to initiate
the second access.
The EAC command memory array is not readable by the host system and has no ASO. The EAC examines
the address and data in each write transfer to determine if the write is part of a legal command sequence.
When a legal command sequence is complete the EAC will initiate the appropriate EA.
OE
), whichever occurs latest, the data outputs will provide valid read data from the currently active address
Asynchronous Read Operations on page
D a t a
OE
GL-S MirrorBit
) before valid data is available.
S h e e t
80.
®
MAX
PACC
Family
to A4 address signals change to a new value, a new
) than a Random Read access.
CE
), address stable (t
CE
) is the delay from stable CE# to valid
ACC
) is equal to the delay from
ACC
), or OE# active
MAX
to A4 address
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