ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet
ST72T311J2T6
Specifications of ST72T311J2T6
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ST72T311J2T6 Summary of contents
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TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS User Program Memory (OTP/EPROM 16K bytes Data RAM: 384 to 512 bytes including 256 bytes of stack Master Reset and Power-On Reset Low Voltage Detector Reset ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72E311 ST72T311 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72T311 HCMOS Microcontroller Unit (MCU member of the ST7 family. The device is based on an industry-standard 8-bit core and features an enhanced instruction set. The device is normally operated ...
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PIN DESCRIPTION Figure 2. 64-Pin Thin QFP Package Pinout PE4 1 PE5 2 PE6 3 PE7 4 (EI2) PB0 5 (EI2) PB1 6 ...
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ST72E311 ST72T311 Table 1. ST72T311Nx Pin Description Pin n° Pin n° Pin Name QFP64 SDIP56 1 49 PE4 2 50 PE5 3 51 PE6 4 52 PE7 5 53 PB0 6 54 PB1 7 55 PB2 8 56 PB3 9 ...
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Pin n° Pin n° Pin Name QFP64 SDIP56 45 33 PA2 46 34 PA3 DD_1 SS_1 49 37 PA4 50 38 PA5 51 39 PA6 52 40 PA7 TEST ...
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ST72E311 ST72T311 Pin n° Pin n° Pin Name QFP44 SDIP42 19 14 PF6/ICAP1_A 20 15 PF7/EXTCLK_A 21 V DD_0 22 V SS_0 23 16 PC0/OCMP2_B 24 17 PC1/OCMP1_B 25 18 PC2/ICAP2_B 26 19 PC3/ICAP1_B 27 20 PC4/MISO 28 21 PC5/MOSI ...
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EXTERNAL CONNECTIONS The following figure shows the recommended ex- ternal connections for the device. The V pin is only used for programming OTP PP and EPROM devices and must be tied to ground in user mode. The 10 nF ...
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ST72E311 ST72T311 1.4 MEMORY MAP Figure 7. Program Memory Map 0000h HW Registers (see 007Fh 0080h 01FFh 512 Bytes RAM 027Fh 0200h / 0280h Reserved BFFFh C000h E000h 8K Bytes Program Memory FFDFh FFE0h Interrupt & Reset Vectors (see FFFFh ...
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Table 4. Hardware Register Memory Map Register Address Block Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h 0004h PCDR 0005h Port C PCDDR 0006h PCOR 0007h 0008h PBDR 0009h Port B PBDDR 000Ah PBOR 000Bh 000Ch PEDR 000Dh ...
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ST72E311 ST72T311 Register Address Block Label 0031h TACR2 0032h TACR1 0033h TASR 0034h-0035h TAIC1HR TAIC1LR TAOC1HR 0036h-0037h TAOC1LR 0038h-0039h Timer A TACHR TACLR 003Ah-003Bh TAACHR TAACLR 003Ch-003Dh TAIC2HR TAIC2LR 003Eh-003Fh TAOC2HR TAOC2LR 0040h 0041h TBCR2 0042h TBCR1 0043h TBSR TBIC1HR ...
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OPTION BYTE The user has the option to select software watch- dog or hardware watchdog (see description in the Watchdog chapter). When programming EPROM or OTP devices, this option is selected in a menu by the user of the ...
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ST72E311 ST72T311 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes ...
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CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...
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ST72E311 ST72T311 CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next ...
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CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a crystal or ceramic reso- nator external clock signal to drive the inter- nal oscillator. The internal clock (f from ...
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ST72E311 ST72T311 3.2 RESET 3.2.1 Introduction There are four sources of Reset: – RESET pin (external source) – Power-On Reset (Internal source) – WATCHDOG (Internal Source) – Low Voltage Detection Reset (internal source) The Reset Service Routine vector is located ...
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RESET (Cont’d) 3.2.4 Low Voltage Detector Reset The on-chip Low Voltage Detector (LVD) gener- ates a static reset when the supply voltage is be- low a reference value. The LVD functions both during power-on as well as when the power ...
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ST72E311 ST72T311 4 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown ...
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INTERRUPTS (Cont’d) Figure 17. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION N I BIT SET? Y FETCH NEXT INSTRUCTION N IRET? Y LOAD PC FROM INTERRUPT VECTOR RESTORE PC FROM STACK THIS CLEARS I BIT BY DEFAULT ...
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ST72E311 ST72T311 Table 6. Interrupt Mapping Source Description Block RESET Reset TRAP Software NOT USED NOT USED EI0 Ext. Interrupt (Ports PA0:PA3) EI1 Ext. Interrupt (Ports PF0:PF2) EI2 Ext. Interrupt (Ports PB0:PB3) EI3 Ext. Interrupt (Ports PB4:PB7) NOT USED Transfer ...
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POWER SAVING MODES 4.4.1 Introduction There are three Power Saving modes. Slow Mode is selected by setting the relevant bits in the Mis- cellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions. 4.4.2 ...
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ST72E311 ST72T311 POWER SAVING MODES (Cont’d) 4.4.4 Halt Mode The Halt mode is the MCU lowest power con- sumption mode. The Halt mode is entered by exe- cuting the HALT instruction. The internal oscillator is then turned off, causing all ...
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MISCELLANEOUS REGISTER The Miscellaneous register allows to select the SLOW operating mode, the polarity of external in- terrupt requests and to output the internal clock. Register Address: 0020h — Read /Write Reset Value: 0000 0000 (00h) 7 PEI3 PEI2 ...
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ST72E311 ST72T311 5 ON-CHIP PERIPHERALS 5.1 I/O PORTS 5.1.1 Introduction The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – analog signal input (ADC) – alternate signal input/output for ...
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I/O PORTS (Cont’d) 5.1.2.4 Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multi- plexer (controlled by the ADC registers) switches the analog voltage present on the ...
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ST72E311 ST72T311 I/O PORTS (Cont’d) . Figure 21 I/O Block Diagram ALTERNATE OUTPUT DR LATCH DDR LATCH OR LATCH ( ABLE BELOW OR SEL DDR SEL DR SEL ALTERNATE INPUT POLARITY SEL EXTERNAL INTERRUPT SOURCE (EIx) Table 10. ...
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I/O PORTS (Cont’d) Table 11. Port Configuration Port Pin name 1) PA0:PA2 Port A PA3 PA4:PA7 PB0:PB4 Port B 1) PB5:PB7 Port C PC0:PC7 PD0:PD5 Port D 1) PD6:PD7 PE0:PE1 Port E 1) PE4:PE7 PF0:PF2 Port F PF4, PF6, PF7 ...
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ST72E311 ST72T311 I/O PORTS (Cont’d) 5.1.4 Register Description 5.1.4.1 Data registers Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Port D Data Register (PDDR) Port E Data Register (PEDR) Port F Data Register ...
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I/O PORTS (Cont’d) Table 12. I/O Port Register Map Address Register 7 Label (Hex.) 0000h PADR D7 0001h PADDR DD7 0002h PAOR O7 0004h PCDR D7 0005h PCDDR DD7 0006h PCOR O7 0008h PBDR D7 0009h PBDDR DD7 000Ah PBOR ...
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ST72E311 ST72T311 5.2 WATCHDOG TIMER (WDG) 5.2.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to ...
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WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see ...
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ST72E311 ST72T311 Table 14. WDG Register Map Address Register Label (Hex.) WDGCR 2A Reset Value WDGSR 2B Reset Value 34/101 WDGA ...
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TIMER 5.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two input sig- nals ( ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) Figure 23. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 ICIE OCIE TOIE FOLV2 FOLV1 (Control ...
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TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read Byte value at t0 ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) Figure 24. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 25. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL ...
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TIMER (Cont’d) 5.3.3.3 Input Capture In this section, the index may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) Figure 27. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 28. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ...
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TIMER (Cont’d) 5.3.3.4 Output Compare In this section, the index may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the reg- ister, the output compare function is inhibited until the register is also written the ...
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TIMER (Cont’d) Figure 30. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i =1) Figure 31. Output Compare Timing ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) 5.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses ...
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TIMER (Cont’d) Figure 32. One Pulse Mode Timing Example FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 33. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) 5.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width ...
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TIMER (Cont’d) 5.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) 5.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input ...
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TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 LOW ...
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ST72E311 ST72T311 16-BIT TIMER (Cont’d) Table 16. 16-Bit Timer Register Map and Reset Values Address Register 7 Name (Hex.) TimerA: 32 CR1 ICIE TimerB: 42 Reset Value 0 TimerA: 31 CR2 OC1E TimerB: 41 Reset Value 0 TimerA ...
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SERIAL COMMUNICATIONS INTERFACE (SCI) 5.4.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range ...
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ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 34. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE ILIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU /16 54/101 54 Read Received ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.4.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1.. It contains 6 dedicated reg- isters: – Two control registers (CR1 & CR2) – A status register (SR) – A ...
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ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.4.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.4.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...
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ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 36. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /2 /PR /16 58/101 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.4.4.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: f CPU (32 PR with: PR ...
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ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.4.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving until ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.4.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content ...
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ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register performs ...
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ST72E311 ST72T311 SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR 7 ...
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SERIAL PERIPHERAL INTERFACE (SPI) 5.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices ...
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ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 38. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS 66/101 66 Internal Bus DR SPIF WCOL SPIE SPE MASTER CONTROL SERIAL CLOCK GENERATOR IT request ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.4 Functional Description Figure 1 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to ...
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ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a sequence of eight ...
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ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 40. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- pens, the transfer ...
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ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an MCU as the ...
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ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.5.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is ...
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ST72E311 ST72T311 SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer ...
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Table 19. SPI Register Map and Reset Values Address Register 7 Name (Hex Reset Value x CR SPIE 22 Reset Value 0 SR SPIF 23 Reset Value ...
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ST72E311 ST72T311 5.6 8-BIT A/D CONVERTER (ADC) 5.6.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input ...
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A/D CONVERTER (ADC) (Cont’d) 5.6.3 Functional Description The high level reference voltage V connected externally to the V DD reference voltage V must be connected exter- SSA nally to the V pin. In some devices (refer to de- SS ...
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ST72E311 ST72T311 8-BIT A/D CONVERTER (ADC) (Cont’d) 5.6.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO - ADON 0 - Bit 7 = COCO Conversion Complete This bit is set by hardware cleared ...
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INSTRUCTION SET 6.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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ST72E311 ST72T311 ST7 ADDRESSING MODES (Cont’d) 6.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt ...
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ST7 ADDRESSING MODES (Cont’d) 6.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST72E311 ST72T311 6.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL ...
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ST72E311 ST72T311 INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2’s compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF ...
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ELECTRICAL CHARACTERISTICS 7.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...
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ST72E311 ST72T311 7.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage DD f Oscillator Frequency OSC Note 1) A safe reset (with Low Voltage Detector option) is not guaranteed at 16 MHz. 2) A/D operation ...
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DC ELECTRICAL CHARACTERISTICS (T = -40°C to +125°C and Symbol Parameter Input Low Level Voltage V IL All Input pins Input High Level Voltage V IH All Input pins 1) Hysteresis Voltage V HYS All Input ...
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ST72E311 ST72T311 7.4 RESET CHARACTERISTICS o (T =-40...+125 C and V =5V±10% unless otherwise specified Symbol Parameter R Reset Weak Pull- Pulse duration generated by watch- t RESET dog and POR reset Minimum pulse duration to ...
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PERIPHERAL CHARACTERISTICS (Cont’ -40°C to +125°C and Symbol Parameter T Sample Duration SAMPLE Res ADC Resolution DLE Differential Linearity Error* ILE Integral Linearity Error* V Analog Input Voltage AIN Supply current rise I ADC during ...
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ST72E311 ST72T311 PERIPHERAL CHARACTERISTICS (Cont’d) Figure 46. ADC Conversion characteristics 255 254 253 252 251 250 code out LSB (ideal Offset Error OSE 92/101 Offset Error ...
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PERIPHERAL CHARACTERISTICS (Cont’d) Ref. Symbol Parameter f SPI frequency SPI 1 t SPI clock periode SPI 2 t Enable lead time Lead 3 t Enable lag time Lag 4 t Clock (SCK) high time SPI_H 5 t Clock (SCK) low ...
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ST72E311 ST72T311 PERIPHERAL CHARACTERISTICS (Cont’d) Measurement points are Figure 48. SPI Master Timing Diagram CPHA=0, CPOL=1 SS (INPUT) SCK (OUTPUT) MISO (INPUT) 6 MOSI (OUTPUT) 10 Figure 49. SPI Master Timing Diagram CPHA=1, CPOL=0 SS (INPUT) ...
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PERIPHERAL CHARACTERISTICS (Cont’d) Measurement points are Figure 51. SPI Slave Timing Diagram CPHA=0, CPOL=0 SS (INPUT) 2 SCK (INPUT) 4 MISO HIGH-Z D7-OUT (OUTPUT) 8 MOSI D7-IN (INPUT) 6 Figure 52. SPI Slave Timing Diagram CPHA=0, ...
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ST72E311 ST72T311 8 GENERAL INFORMATION 8.1 EPROM ERASURE EPROM version devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It ...
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PACKAGE MECHANICAL DATA Figure 55. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2 D Figure 56. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width 0.015 GAGE ...
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ST72E311 ST72T311 Figure 57. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2 D Figure 58. 56-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width 98/101 0.015 GAGE ...
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Figure 59. 64-Pin Thin Quad Flat Package D D1 Figure 60. 44-Pin Thin Quad Flat Package Dim ...
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ST72E311 ST72T311 8.3 ORDERING INFORMATION Each device is available for production in user pro- grammable version (OTP). OTP devices are shipped to customer with a default blank content FFh. There is one common EPROM version for Figure 61. OTP User ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...